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CAN Bus Power

CAN bus power — full sheet
Hardware version

WTI400 v1.2 — In service — installed on test vessel

Overview​

The CAN bus power circuit takes the raw NMEA 2000 bus supply (NET-S, nominally 12 V) and delivers a clean, protected supply rail (VSC) to the rest of the WTI400. Six sequential stages condition the input: primary surge clamping, a resettable fuse and reverse-polarity protection, bulk capacitor buffering, a two-stage LC EMI filter, an over-voltage protection switch, and a secondary output clamp.

This page covers a single sub-circuit — the CAN Bus Power rail — drawn on the can_bus_power KiCad sheet.

Functional specification and design objectives​

The CAN bus power circuit must:

  • withstand NMEA 2000 bus surge events up to ISO 7637-2 Pulse 5b without component damage;
  • block reverse polarity passively — no firmware involvement;
  • provide a resettable overload fuse that restores automatically after a fault clears;
  • suppress conducted EMI on the supply rail before it reaches the downstream regulators;
  • disconnect VSC if bus voltage rises above the LP2951 wind transducer LDO's safe operating range; and
  • deliver VSC within 300 mV of NET-S under normal operating current.

CAN Bus Power​

CAN bus power — full sheet, conditioning stages 1–6 from NET-S to VSC. Zoom out to see the full sheet.

How it works​

The NMEA 2000 bus delivers power on NET-S (positive) and NET-C (ground). The WTI400 is bus-powered: GNDREF is tied directly to NET-C at J2. NET-S is nominally 9–16 V DC under IEC 61162-3, with a maximum charging voltage of 14.8 V. Surge events — load-dump, cable plug/unplug, or a switching transient elsewhere on the backbone — can reach hundreds of volts for microseconds at J2.

CAN Domain Power Conditioning (Stages 1–4)​

CAN domain power conditioning — TVS/MOV clamp, fuse + reverse-polarity Schottky, bulk caps, two-stage LC EMI filter. Zoom out to see the full sheet.
Stage 1 — Primary surge clamping​

Two devices in parallel absorb surge energy before it reaches any active circuitry.

D11 (SM8S36CA) is a bidirectional TVS in a DO-218AB package with a 36 V standoff voltage and 6.6 kW peak pulse power rating. It clamps fast transients — including ISO 7637-2 Pulse 5b — to approximately 58 V during an 8/20 µs surge. The DO-218AB footprint uses copper pads on all layers with four 1 mm through-hole vias for thermal relief during repeated surge events.

M1 (V33MLA1206NH) is a 75 V metal oxide varistor in 1206. MOVs are slower than TVS diodes but absorb more energy across a longer pulse. M1 absorbs the leading edge of slow high-energy transients before D11 needs to clamp.

Stage 2 — Fuse and reverse-polarity protection​

F1 (BSMD1812-050-60V) is a 500 mA / 60 V PTC resettable fuse in 1812. A PTC is preferred over a one-shot fuse for a marine instrument: a blown fuse mid-passage leaves the instrument dead with no means of recovery. After a fault clears, F1 cools and resets automatically. The 500 mA hold current at 25 °C gives a 7× margin over the 65 mA continuous operating current — accidental trips from normal operation are not possible.

D9 (SS34) is a 40 V / 3 A Schottky diode in SMA, wired in series on the high-side rail immediately after F1. It blocks reverse polarity passively: if NET-S and NET-C are swapped, D9 prevents current from flowing. The Schottky forward voltage (~380 mV at 65 mA) contributes to the voltage drop budget.

Stage 3 — Bulk capacitor buffer​

C41 and C42 (2 × 22 µF / 100 V, X7R, 2220) provide 44 µF of bulk capacitance at the post-fuse rail, decoupling cable impedance and storing energy during the brief window while D11 is clamping a surge event.

R43 (100 mΩ) damps LC resonance between the bulk capacitor bank and the EMI filter inductors that follow. Without it, the undamped series resonance at ~60 kHz would produce an impedance peak, degrading filter attenuation near that frequency. R39 (220 mΩ) damps the resonance between the bulk stage and the first filter inductor. Both are passive damping resistors — they carry load current but dissipate only 0.4 mW and 0.9 mW respectively at 65 mA operating current.

R42 (100 kΩ) bleeds C41/C42 to zero when power is removed, preventing VSC from remaining live after the bus is disconnected.

Stage 4 — Two-stage LC EMI filter​

A cascaded LC ladder suppresses conducted EMI on the supply rail. Two filter stages are used because a single stage would require impractically large inductors to achieve the same attenuation.

First stage: L3 (1 µH, 3.5 A rated) with C39 (1 µF), C36 (4.7 µF), and C37 (4.7 µF) as shunt capacitors to GNDREF. The three shunt capacitors in parallel give an effective nominal capacitance of 10.7 µF, derated to approximately 6.3 µF at 12 V DC bias (X7R characteristic).

Second stage: L2 (4.7 µH, 2.1 A rated) with C33 (22 µF), C32 (100 nF), and C34 (100 nF). C33 derated to ~8.8 µF at 12 V; C32/C34 provide high-frequency shunting at 90 nF each. C32 also decouples the V_P1 node.

The filter output is the local net V_P1, which feeds the OVP switch.

StageLC_eff at 12 Vf_c
11 µH6.3 µF63 kHz
24.7 µH9.0 µF24 kHz
X7R DC bias derating

X7R MLCC capacitance falls significantly with applied DC voltage. All filter capacitor values above are rated at 100 V; at 12 V operating voltage the effective capacitance is approximately 60–75% of the nominal value. Filter corner frequencies are calculated on the derated values. Measure actual capacitance at bring-up to verify.

Over-voltage Protection (Stages 5–6)​

Over-voltage protection — Q2 high-side switch, Q3 comparator, R27/R28 divider, R25/R26 gate network, C28 hysteresis, D3 gate clamp, D2 secondary clamp. Zoom out to see the full sheet.
Stage 5 — OVP comparator and high-side switch​

The OVP circuit disconnects VSC from V_P1 if the bus voltage rises above approximately 18.6 V. It protects the LP2951 wind transducer LDO (U13, 30 V absolute maximum input): the 18.6 V trip point provides 11.4 V of margin below that limit. Without OVP, a sustained bus fault — a faulty charger or a wrong supply connected to the backbone — could drive the bus toward or beyond 30 V and damage U13. The LMR51610 buck converter (U2) is rated to 65 V and does not require this protection.

OVP origin

The same OVP topology was first used in the MDD400, where it protects the INA219 current monitor. The INA219 is not present in the WTI400, but the LP2951 (30 V maximum) provides the same design constraint.

Q2 (PMV240SPR) is a P-channel MOSFET in SOT-23, wired as a series high-side switch between V_P1 (source) and VSC (drain). Under normal conditions, R26 (22 kΩ) pulls Q2's gate to GNDREF, giving V_GS ≈ −12 V — Q2 is fully on.

Q3 (MMBTA56LT1G) is a PNP BJT in SOT-23. Its emitter connects to V_P1; its base connects to the midpoint of the voltage divider formed by R28 (2.4 kΩ, upper arm, V_P1 to base) and R27 (68 kΩ, lower arm, base to GNDREF). When V_P1 rises to the OVP threshold, the voltage at Q3's base rises proportionally, but the emitter (at V_P1) rises faster. Once the base-emitter voltage exceeds ~0.635 V, Q3 turns on; its collector current through R25 (4.7 Ω) raises Q2's gate toward V_P1, turning Q2 off and disconnecting VSC.

C28 (100 nF) in parallel with R27 adds a 6.8 ms hysteresis time constant, preventing oscillation at the trip threshold.

The OVP threshold is:

V_threshold = V_BE × (R27 + R28) / R28
            = 0.635 V × (68,000 + 2,400) / 2,400
            = 18.6 V  (nominal, 25 °C)

OVP has been verified on both MDD400 and WTI400 prototypes — confirmed disconnect at 18.6 V.

V_BE decreases with temperature at approximately 2 mV/°C, causing the threshold to drift:

TemperatureV_BEV_thresholdMargin vs 14.8 V max
25 °C635 mV18.6 V+3.8 V
50 °C585 mV17.2 V+2.4 V
85 °C515 mV15.1 V+0.3 V

At 85 °C the margin above the NMEA 2000 maximum charging voltage (14.8 V) is 300 mV — see Gaps.

D3 (BZT52C7V5S) is a 7.5 V Zener between Q2's source (V_P1) and gate. During a D11-clamped surge, V_P1 peaks at ~58 V while Q2's gate is held near 0 V by R26. Without D3, V_GS would reach −58 V against a ±20 V rating. D3 clamps V_GS to −7.5 V throughout the event.

Stage 6 — Secondary output clamp​

D2 (PESD15VL1BA) is a 15 V / 200 W bidirectional TVS across VSC and GNDREF. It catches fast transients that pass through Q2 before the OVP comparator can respond, providing a final protective barrier for the downstream regulators.

Performance​

Voltage drop budget (NET-S to VSC)​

ElementDrop at 65 mADrop at 115 mA peak
F1 (PTC cold, ~0.5 Ω)33 mV58 mV
D9 (Schottky V_F)380 mV430 mV
R43 (100 mΩ)7 mV12 mV
R39 (220 mΩ)14 mV25 mV
Q2 (R_DS(on) = 365 mΩ)24 mV42 mV
Total458 mV567 mV

At NMEA 2000 minimum bus voltage (9.0 V): VSC_min ≈ 8.54 V. The LP2951 in the 8v4 variant (Raymarine) requires ≥ 8.95 V input; it will lose regulation at absolute minimum bus voltage under full transducer load. The 6v8 variant (B&G) passes with 1.35 V margin. This is an accepted design constraint — typical operating bus voltage is 12–13 V.

PCB Layout​

All can_bus_power components are placed on F.Cu (front copper). A solid GNDREF plane fills In1.Cu across the full board extent, and a large F.Cu GNDREF pour (66.4–98.1 × 62.8–137.6 mm) covers the entire circuit area, giving every TVS, MOV, and reference component a short, low-inductance return. The circuit occupies the left column of the board (x ≈ 70–95 mm) and is laid out in reverse power-flow order — OVP output at the top (low Y), input surge clamp at the bottom (high Y). VSC leaves the OVP output region as a 0.6 mm trace routed ~45.8 mm down B.Cu to the load distribution area, keeping the front copper uncongested.

  • Surge clamp at the connector. M1 (MOV) is placed 8.5 mm from J2 to provide early energy absorption for slow transients. D11 (the 6.6 kW TVS, DO-218AB) sits 16.1 mm from J2 — placed adjacent to F1 (0.5 mm) rather than at the connector, because J2's mounting flange precludes closer placement. This is an accepted physical constraint, identified during the MDD400 V2.9 review and carried forward to all WTI400 revisions; the 1.8 mm NET-S trace (adding ~11 nH) is the minimum achievable given the connector geometry. D11's *.Cu multi-layer pads (9.0 × 10.0 mm primary, plus four 1 × 1 mm through-hole vias) spread surge heat into the In1.Cu and F.Cu planes.
  • Fuse placement. F1 is 7.7 mm from D11 — closer than recommended for a device that dissipates surge energy as heat — and 6.7 mm from D9, with adequate inductor separation (10.8 mm to L3, 16.5 mm to L2). The D11 proximity is flagged for surge-thermal verification (see Gaps).
  • EMI filter inductors. L2 (4.7 µH) and L3 (1 µH) share the same axis with a 5.95 mm centre-to-centre spacing, giving a 1.95 mm edge-to-edge gap — 0.05 mm short of the 2 mm keepout. The nearest other inductor (L1) is 33.7 mm away. Possible magnetic cross-coupling between the two filter inductors is flagged for the next layout revision (see Gaps).
  • Power-path routing. The main path NET-S → F1 → D9 → C41/C42 → L3 → L2 → V_P1 → Q2 → VSC is carried predominantly by named copper pour zones (Net-(D9-A), Net-(D9-K), Net-(C41-Pad1), Net-(L2-Pad1), V_P1), all wider than the 0.5 mm minimum. Bulk caps C41/C42 connect to the D9-cathode pour with short, wide GNDREF returns; the 0.2 mm gate-drive traces (Q3 collector → Q2 gate, via R25/D3) are signal-level (< 5 mA) and acceptable.
  • OVP cluster. D2 (2.7 mm from Q2 drain), D3 (3.0 mm from Q2, forming a tight gate-source clamp loop), and the divider/sense components (R25, R26, R27, R28, C28, Q3) are grouped tightly around Q2 at the top of the circuit. The V_P1 HF bypass caps C32/C34 sit 4.7–6.2 mm from the L2 output pad — beyond the 1 mm guideline but inside the V_P1 copper pour, which provides the low-impedance connection.

Components​

RefValueFunctionDatasheet
D11SM8S36CABidirectional TVS, DO-218AB, 36 V / 6.6 kW — primary surge clampFUXINSEMI SM8S36CA
M1V33MLA1206NHMOV, 1206, 75 V — slow high-energy transient absorberLittelfuse V33MLA1206NH
F1500 mA / 60 VPTC resettable fuse, 1812 — series overload protectionBHFUSE BSMD1812-050-60V
D9SS34Schottky, SMA, 40 V / 3 A — reverse-polarity protectionMSKSEMI SS34-MS
C41, C4222 µF / 100 VX7R 2220 — bulk input capacitors (44 µF combined)PSA FS55X226K101LRG
R43100 mΩ0603 — bulk capacitor ESR damping—
R39220 mΩ0603 — LC filter input damping—
R42100 kΩ0603 — bulk capacitor bleed/discharge—
L31 µH3.5 A / 4.6 A Isat, 4×4 mm — first-stage EMI filter inductorcjiang FHD4012S-1R0MT
C391 µF / 100 VX7R 1206 — first-stage filter shunt capMurata GRM31CR72A105KA01K
C36, C374.7 µF / 100 VX7R 1206 — first-stage filter shunt caps (parallel)Murata GRM31CZ72A475KE11L
L24.7 µH2.1 A / 2.6 A Isat, 4×4 mm — second-stage EMI filter inductorcjiang FHD4012S-4R7MT
C3322 µF / 100 VX7R 2220 — second-stage filter bulk capPSA FS55X226K101LRG
C32, C34100 nF / 100 VX7R 0603 — second-stage filter HF shunt capsMurata GCJ188R72A104KA01D
Q2PMV240SPRP-channel MOSFET, SOT-23, 100 V / 1.2 A — OVP series switchNexperia PMV240SPR
Q3MMBTA56LT1GPNP BJT, SOT-23, 80 V / 500 mA — OVP sense transistoronsemi MMBTA56LT1G
D3BZT52C7V5SZener, SOD-323, 7.5 V — Q2 gate-source clampDiodes Inc BZT52C7V5S-7-F
R282.4 kΩ0603 — OVP divider upper arm (V_P1 to Q3 base)—
R2768 kΩ0603 — OVP divider lower arm (Q3 base to GNDREF)—
C28100 nF / 50 VX7R 0603 — OVP hysteresis capacitor (parallel with R27)—
R254.7 Ω0603 — Q3 collector resistor; limits Q2 gate current—
R2622 kΩ0603 — Q2 gate pull-down; holds Q2 on under normal conditions—
D2PESD15VL1BABidirectional TVS, SOD-323, 15 V / 200 W — secondary VSC clampNexperia PESD15VL1BA

Testing & Verification​

caution

The V1.2 prototype on the test vessel has been bus-powered for approximately 1,000 sea miles. VSC regulates correctly under operational NMEA 2000 bus voltage and no PTC trips, OVP trips, or component failures have been observed. OVP threshold has been verified at 18.6 V on both the WTI400 V1.2 and MDD400 V2.9 prototypes. No quantitative bench measurements have been performed on surge survivability, F1 thermal proximity to D11, L2 cold-start inrush, EMI filter ripple, or filter capacitor DC-bias derating. The following are required.

Hardware bring-up (rig at the bench):

  • Reverse polarity — Apply −12 V to NET-S. Pass if VSC remains at 0 V and no components become warm.
  • Normal operation — Apply 12 V; measure VSC. Pass if VSC ≈ 11.5 V.
  • OVP trip — Slowly raise supply voltage. Pass if VSC drops to 0 V between 17.5 V and 19.5 V with no oscillation at the threshold (verified at 18.6 V on prototypes).
  • OVP hysteresis — After trip, slowly reduce supply voltage. Pass if VSC recovers cleanly at a voltage measurably below the trip point.
  • PTC fuse — Short VSC briefly. Pass if F1 trips and the board powers up again without intervention after the fault clears.
  • Bleed resistor — Remove supply; measure VSC discharge time. Pass if VSC reaches < 1 V in approximately 4.4 s (R42 × 44 µF).
  • EMI filter ripple — Scope VSC with a 65 mA load. Pass if supply ripple is below the LMR51610 VIN ripple tolerance.
  • Filter capacitance at bias — Measure C33, C36, C37, C39 at 12 V DC bias. Record actual values and compare against derated filter corner frequency calculations.
  • Surge — Apply an ISO 7637-2 Pulse 5b transient (or bench equivalent) to NET-S. Pass if VSC remains stable and all components survive.
  • F1 thermal proximity to D11 — Run an IEC 61000-4-5 surge sequence and confirm F1 body temperature stays below 70 °C post-surge.
  • L2 cold-start inrush — Confirm peak current through L2 at power-on stays below the 2.6 A saturation rating.

Gaps & next version​

Before next production run

  • F1 thermal proximity to D11 — F1 is 7.7 mm from D11 — closer than recommended for a device that dissipates surge energy as heat. Run an IEC 61000-4-5 surge sequence and confirm F1 body temperature stays below 70 °C post-surge; if it exceeds 70 °C, add a copper thermal break in the NET-S flood between D11 and F1.
  • L2 cold-start inrush — Confirm peak current through L2 at power-on stays below the 2.6 A saturation rating.
  • L2 / L3 magnetic coupling — Measure in-circuit LCR on L2 and L3 with both installed; if mutual coupling exceeds ~5%, increase spacing in the next layout revision.
  • D11 sourcing for production — Qualify a Littelfuse or STMicro equivalent SM8S36CA for CE / ABYC certification; the current FUXINSEMI part is suitable for prototype but not preferred for production compliance.

Next version (V1.3)

  • OVP threshold margin at temperature — At 85 °C the OVP threshold reaches 15.1 V — only 300 mV above the 14.8 V NMEA 2000 maximum. Either raise the 25 °C trip point (decrease R28 or increase R27) or replace the divider-only comparator with a voltage reference for temperature-stable operation.
  • L2 / L3 body spacing — Current edge-to-edge gap is 1.95 mm — 0.05 mm short of the 2 mm keepout. Increase centre-to-centre spacing from 5.95 mm to ≥ 6.05 mm in the next layout revision.
  • Over-temperature disconnect — Add a 2-component mod: a normally-closed thermal switch in series between R26 and GNDREF plus a 100 kΩ pull-up from Q2's gate to source. Switch placement must be adjacent to the hottest component (Q2 or L2 / L3).

References​