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Tasks

Hardware version

MDD400 v2.9 — Fabricated prototype, bench-test phase. Live task list for the MDD400 V2.9 hardware revision and the next-version (V2.10) backlog. Underlying data: tasks.json — hand-maintained, edited as work progresses.

Every actionable task for MDD400 V2.9 — verification work against the current hardware + the next-version (V2.10) backlog — across all four product domains (hardware, firmware, housing, compliance). Click a row to expand details; click a column header to sort; hover any badge for help. See Legend below for full field meanings, or Editing workflow for how to update entries.

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By kind:Verification 83Next version 43
By category:Hardware 121Compliance 5
Status:Kind:Category:Sub-circuit / module:
Kind ▲CategorySub-circuit / moduleTask / descriptionStatusDateResult
Verification v2.9HardwareAmbient Light Sensor
Bright reading
drive a known bright source; reading should be within ±20 % of a reference lux meter at the housing surface.
To do——
Verification v2.9HardwareAmbient Light Sensor
Brightness lookup table re-fit
characterise the V2.9 housing aperture's transfer function from outside illuminance to OPT3004 raw reading at multiple ambient levels (direct sunlight, indoor office, twilight, night helm, total dark). Re-fit the lookup so the firmware brightness loop produces the same perceived display brightness vs ambient as the prior hardware revision did. Apply DGUS II step-boundary hysteresis.
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Verification v2.9HardwareAmbient Light Sensor
Dark reading
cover the housing aperture; reading should fall below 1 lux.
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Verification v2.9HardwareAmbient Light Sensor
Full-range sweep
dark → indoor → direct sunlight; no stuck-state or skipped-range behaviour from auto-range mode.
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Verification v2.9HardwareAmbient Light Sensor
I²C addressing
read manufacturer ID at 0x44.
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Verification v2.9HardwareBuzzer Driver
Current draw at full duty
peak / average VDD-side current consistent with calculated ~313 mA peak / ~156 mA average.
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Verification v2.9HardwareBuzzer Driver
Default-off at power-up
no audible chirp during the first 500 ms after VDD comes up with AUDIO_PWM unconnected.
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Verification v2.9HardwareBuzzer Driver
Default-off recovery
tone stops immediately when AUDIO_PWM is released to high-impedance.
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Verification v2.9HardwareBuzzer Driver
Single-tone correctness
2 kHz square wave produces audible tone at expected loudness.
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Verification v2.9HardwareBuzzer Driver
Tone-palette sweep
1 kHz to 4 kHz in 100 Hz steps; record any resonant peaks / dips for firmware library tuning.
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Verification v2.9HardwareCAN Bus Power Protection
Bleed resistor
Remove supply; pass if VS+ reaches < 1 V in approximately 4.4 s (R54 × 44 µF).
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Verification v2.9HardwareCAN Bus Power Protection
D7 clamp under transient
Inject a representative fast transient onto VS+. Pass if VS+ stays below the INA219's 40 V VS abs-max.
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Verification v2.9HardwareCAN Bus Power Protection
EMI filter ripple
Scope VS+ at 242 mA load. Pass if supply ripple stays below the LMR51610 V_IN tolerance.
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Verification v2.9HardwareCAN Bus Power Protection
F1 thermal proximity to D10
After an IEC 61000-4-5 surge sequence, confirm F1 body temperature stays below 70 °C.
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Verification v2.9HardwareCAN Bus Power Protection
Filter capacitance at bias
Measure C43, C45, C46, C47 at 12 V DC bias; record actual values against the derated filter corner-frequency calculations.
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Verification v2.9HardwareCAN Bus Power Protection
INA219 current reading
At 242 mA nominal load, confirm the INA219 reading is within ±5 % of a bench ammeter cross-check.
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Verification v2.9HardwareCAN Bus Power Protection
L3 cold-start inrush
Confirm peak current through L3 at power-on stays below the 2.6 A saturation rating.
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Verification v2.9HardwareCAN Bus Power Protection
Normal operation
Apply 12 V. Pass if VS+ ≈ 11.25 V (within the ~750 mV drop budget).
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Verification v2.9HardwareCAN Bus Power Protection
OVP hysteresis
After trip, slowly reduce supply. Pass if VS+ recovers cleanly below the trip point.
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Verification v2.9HardwareCAN Bus Power Protection
OVP trip
Slowly raise supply voltage. Pass if VS+ drops to 0 V between 17.5 V and 19.5 V with no oscillation. *(Verified at 18.6 V on both MDD400 and WTI400 prototypes.)*
Done—Verified at 18.6 V on both MDD400 and WTI400 prototypes.
Verification v2.9HardwareCAN Bus Power Protection
PTC fuse
Briefly short VS+. Pass if F1 trips and the board recovers without intervention after the fault clears.
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Verification v2.9HardwareCAN Bus Power Protection
Reverse polarity
Apply −12 V to NET-S. Pass if VS+ stays at 0 V with no component heating.
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Verification v2.9HardwareCAN Transceiver
Bus fault survivability
Apply a brief over-voltage to CANH / CANL at J2; confirm U10 clamps and U5 survives. Note the 4 V clamp-vs-spec margin.
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Verification v2.9HardwareCAN Transceiver
Bus idle — recessive state
With TWAI_EN LOW, measure CANH and CANL at J2. Pass if both sit at approximately 2.5 V.
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Verification v2.9HardwareCAN Transceiver
Receive on live network
Connect to an NMEA 2000 network; capture traffic with a CAN analyser. Pass if frames are received at 250 kbps with no error frames.
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Verification v2.9HardwareCAN Transceiver
Transceiver enable
Assert TWAI_EN HIGH. Pass if U5 enters normal mode with no bus disturbance on a scope.
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Verification v2.9HardwareCAN Transceiver
Transmit on live network
Send a test PGN. Pass if the frame appears on the network and is acknowledged by another node.
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Verification v2.9HardwareCAN Transceiver
TWAI loopback
Configure the TWAI peripheral in self-test/loopback mode; transmit a frame. Pass if received without error.
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Verification v2.9HardwareCAN Transceiver
TXD default
Before TWAI initialised, measure TXD at U5 pin 1. Pass if HIGH (R17 holding recessive).
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Verification v2.9HardwareDisplay Interface
Brightness lookup re-calibration
the V2.9 housing and ALS placement differ from the prior hardware revision. The existing ALS-reading → DGUS II brightness step lookup table must be re-characterised on the V2.9 prototype before the firmware can be deployed on this hardware. Bench-test at multiple ambient illuminances (direct sunlight, indoor office, night helm, totally dark) and re-fit the curve. Apply hysteresis at each DGUS II step boundary.
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Verification v2.9HardwareDisplay Interface
Default-off at power-up
VDSP < 50 mV at J4 with DISP_EN unconnected.
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Verification v2.9HardwareDisplay Interface
Hard-reset recovery
drive DISP_EN LOW for 10 ms, then HIGH; T5L re-boots and DGUS II commands resume.
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Verification v2.9HardwareDisplay Interface
Operating-current characterisation
record peak VDD current at several backlight settings; confirm well within Q4 (4.2 A) and FB3 (3 A) ratings. (Performance review used 400 mA as a conservative estimate; replace with measured value.)
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Verification v2.9HardwareDisplay Interface
Power-on transition
Q4 gate pulled to ≤ 0.5 V within one GPIO cycle after DISP_EN goes HIGH.
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Verification v2.9HardwareDisplay Interface
UART round-trip and touch-event reception
see the per-sub-circuit bring-up lists above.
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Verification v2.9HardwareDisplay Interface
VDSP rail under display load
within ±2 % of VDD with no dip below 4.85 V, even under animated UI + 100 % backlight.
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Verification v2.9HardwareESP32 Module
BOOT pull-up integrity
Capture ESP_BOOT over a 60 s window during normal operation. Pass if it sits stable at VCC with no glitches.
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Verification v2.9HardwareESP32 Module
EN release timing
Trigger on VCC rising; capture ESP_EN. Pass if ESP_EN crosses 2.48 V ≥ 10 ms after VCC reaches 3.0 V.
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Verification v2.9HardwareESP32 Module
VCC rail under Wi-Fi TX
Probe at U3 pad 2 during a sustained 802.11b TX burst. Pass if the rail stays within ±3 % of 3.30 V with no individual dip below 3.10 V.
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Verification v2.9HardwareLED Indicator
Default-on at power-up
Apply VCC with LED_EN unconnected (or firmware-controlled GPIO held high-impedance). Pass if D2 illuminates within a few milliseconds of VCC reaching its nominal value, before firmware starts.
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Verification v2.9HardwareLED Indicator
Firmware-off control
Boot firmware; configure LED_EN as a GPIO output and drive it HIGH. Pass if D2 fully extinguishes within one GPIO cycle and stays off until LED_EN is released or driven LOW.
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Verification v2.9HardwareLED Indicator
I_LED measurement
Probe across R14 with Q1 on. Calculate I<sub>LED</sub> from V<sub>R14</sub> / 390 Ω. Pass if I<sub>LED</sub> is between 2.5 mA and 3.5 mA (allowing for amber LED V<sub>F</sub> spread).
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Verification v2.9HardwareLED Indicator
Visibility check
Confirm D2 is clearly visible through the front-panel housing aperture at typical operating viewing angle. If too dim, reduce R14 in a future revision; if too bright, increase R14.
To do——
Verification v2.9HardwareLegacy Serial Interface
38400 baud (NMEA 0183 HS) test pattern
UART RX captures correct framing with no errors.
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Verification v2.9HardwareLegacy Serial Interface
4800 baud rising edge
ST_SIG reaches ≥ 80 % VST within 50 µs (rise-time assist functioning).
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Verification v2.9HardwareLegacy Serial Interface
4800 baud test pattern
UART RX captures correct framing with no errors.
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Verification v2.9HardwareLegacy Serial Interface
58 V transient on ST_SIG (clamped upstream)
Gate driver and Q10 survive.
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Verification v2.9HardwareLegacy Serial Interface
9600 baud rising edge
ST_SIG reaches ≥ 80 % VST within 30 µs (assist effective after C48 rework).
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Verification v2.9HardwareLegacy Serial Interface
Apply 12 V to J3 pin 1
VST regulates at 12.0 ± 0.5 V.
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Verification v2.9HardwareLegacy Serial Interface
Apply 16 V to J3 pin 1
VST regulates at 12.0 ± 0.5 V; U11 junction ΔT &lt; 2 °C.
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Verification v2.9HardwareLegacy Serial Interface
Apply 9 V to J3 pin 1
VST ≈ 8.1 V (dropout); LED current still ≥ 2.9 mA and ST_RX responds to bus signal.
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Verification v2.9HardwareLegacy Serial Interface
Force LOW via 1 kΩ to GND
ST_RX ≤ 0.4 V.
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Verification v2.9HardwareLegacy Serial Interface
Idle bus
ST_RX ≈ VCC (≥ 2.9 V).
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Verification v2.9HardwareLegacy Serial Interface
NMEA 0183 listener compliance
Input current at J3 pin 3 = 2.0 V stays ≤ 2.0 mA (target ~0.36 mA).
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Verification v2.9HardwareLegacy Serial Interface
Reverse polarity / swapped pins
Apply −12 V or swap pin 1 and pin 2. Pass if VST = 0 V and no component damage.
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Verification v2.9HardwareLegacy Serial Interface
ST_EN HIGH (or undriven)
ST_SIG sits at VST (~12 V via R37); transmitter off.
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Verification v2.9HardwareLegacy Serial Interface
ST_EN LOW, ST_TX HIGH
ST_SIG = VST; Q10 not conducting.
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Verification v2.9HardwareLegacy Serial Interface
ST_EN LOW, ST_TX LOW
ST_SIG &lt; 50 mV; Q10 conducting and bus pulled LOW.
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Verification v2.9HardwareLegacy Serial Interface
VST = 16 V
D9 (V_Z = 15 V) zener leakage / dissipation stays ≤ 200 mW.
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Verification v2.9HardwareLegacy Serial Interface
VST = 9 V (dropout) RX behaviour
I_LED ≥ 2.0 mA; ST_RX transitions correctly with no missed edges.
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Verification v2.9HardwarePCB Markings & Compliance
Compliance-mark legibility
Photograph all silkscreen marks at typical helm-position lighting. Pass if every mark is clearly readable at arm's length.
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Verification v2.9HardwarePCB Markings & Compliance
Copyright year currency
S8 reads "© 2025". The V2.10 production run should refresh the year if it's manufactured after 2026.
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Verification v2.9HardwarePCB Markings & Compliance
Pick-and-place fiducial recognition
Confirm at the start of the V2.10 production assembly run that the pick-and-place machine successfully detects FID1–FID4 on both F.Cu and B.Cu without manual override.
To do——
Verification v2.9HardwarePCB Markings & Compliance
QR-code URL resolution
Scan S6 with a phone. Pass if the resolved URL matches the live docs URL exactly. *(Earlier MDD400 hardware revisions had a `docs.scadys.com` → `docs.scadys.io` URL transition; the V2.9 schematic footprint reads `docs.scadys.io` but verify on the as-fabricated board.)*
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Verification v2.9HardwarePower Monitor
Bus voltage accuracy
within ±1 % against a calibrated DMM.
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Verification v2.9HardwarePower Monitor
Calibrated current accuracy
within ±1 % at full-scale (~485 mA), ±5 % at 10 % FS.
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Verification v2.9HardwarePower Monitor
I²C addressing
read manufacturer ID at 0x40.
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Verification v2.9HardwarePower Monitor
PGA configuration
confirm firmware writes PG1:PG0 = 0b10 (PGA /4).
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Verification v2.9HardwarePower Monitor
Shunt self-heating drift
&lt; ±0.5 % drift over a 30-minute soak at 250 mA peak.
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Verification v2.9HardwarePower Supplies
Dual-converter common-mode EMI pre-scan
Capture conducted-emission spectrum on the VSD input with both converters running. Look for 400 kHz / 800 kHz / 1.2 MHz peaks rising above margin. This is the test that motivates the V2.10 phase-staggering work below.
To do——
Verification v2.9HardwarePower Supplies
IC case temperature soak
10 min worst-case load at 85 °C enclosure ambient (or scaled). Touch-probe U1 and U6. Pass if case &lt; ~95 °C (Tj &lt; ~115 °C). Hotter readings are a strong DRG-package-swap signal.
To do——
Verification v2.9HardwarePower Supplies
Output ripple at full load
100 MHz scope with ≤ 5 mm-tip ground. For VCC sustain an 802.11b TX burst; for VDD set DWIN backlight to 100 %. Pass if &lt; 50 mV pp at 400 kHz on both rails.
To do——
Verification v2.9HardwarePower Supplies
Output-voltage accuracy
Probe VCC at TP1 and VDD at the inductor-side of FB2 with no Wi-Fi or display activity. Pass if 3.30 V ± 2 % (VCC) and 5.00 V ± 2 % (VDD).
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Verification v2.9HardwarePower Supplies
Snubber decision
500 MHz scope on each SW node with low-inductance ground spring; capture rising edge. Pass without snubber if peak ringing &lt; ~1 V above V_in; otherwise populate R7+C9 (VCC) or R23+C24 (VDD).
To do——
Verification v2.9HardwareProgramming Socket
D3 back-feed check
Power the board from its own VDD only; probe J1 pin 1 (V_PROG). Pass if pin 1 measures &lt; 0.1 V above VDD − V_F(D4); any larger reading indicates leakage on the OR'd node.
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Verification v2.9HardwareProgramming Socket
End-to-end programming via ESP-PROG
Flash a known image at 921600 baud through the standard ESP-PROG adapter and cable. Pass if the image flashes cleanly, the device boots, and Wi-Fi associates.
To do——
Verification v2.9HardwareProgramming Socket
U4 thermal soak under Wi-Fi TX
Sustained 802.11b TX for 30 minutes from cold start; record U4 body temperature with a thermocouple every 5 minutes. Pass if peak Tj stays below 110 °C in a 70 °C-ambient soak chamber, or below 80 °C at room ambient. Tj > 110 °C is a strong V2.10 signal to expand the F.Cu pour or add thermal vias.
To do——
Verification v2.9HardwareProgramming Socket
VDD-only operation
Disconnect the ESP-PROG cable; power the board from VDD alone. Pass if the LDO produces 3.30 V ± 2 % and the ESP32 boots normally (confirms the D4 OR'ing path).
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Verification v2.9HardwareTemperature Sensor
ALERT pin reachability
*(optional)* — confirm R62 holds ALERT high at idle and the open-drain output pulls cleanly when triggered.
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Verification v2.9HardwareTemperature Sensor
Hot-soak response
local heat application produces an immediate reading rise.
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Verification v2.9HardwareTemperature Sensor
I²C addressing
read CONFIG register at 0x48; default value 0x60A0 confirms presence.
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Verification v2.9HardwareTemperature Sensor
Long-duration helm-position soak
log temperature at 1 Hz over a representative sun-loaded helm session. Use the data to tune the three firmware thresholds (alert / derate / shutdown).
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Verification v2.9HardwareTemperature Sensor
Room-temperature reading accuracy
within ±2 °C of a reference instrument.
To do——
Next version v2.10HardwareAmbient Light Sensor
OPT3004 INT pull-up
if a future firmware revision wants to interrupt-drive on threshold crossings, the open-drain INT pin needs an external pull-up to V<sub>DD</sub>. Currently absent. Polled mode in current firmware doesn't require it, so this is a forward-looking item.
To do——
Next version v2.10ComplianceBuzzer Driver
CISPR 32 conducted-emission scan including the buzzer drive net
the R10 / C12 / R9 filter is calculated to attenuate harmonics above ~7.2 kHz, but no measurement has been performed. Include the buzzer drive net in the prototype's conducted-emission scan during V2.10 compliance pre-screening.
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Next version v2.10HardwareBuzzer Driver
Re-run the buzzer-filter simulation with V2.9 component values
R10 4.7 Ω, C12 4.7 µF, R9 10 Ω. Record operating conditions (PWM frequency, duty cycle, load impedance). Add the simulation source to `design-docs/`. The waveform images currently sourced from V2.8 old-docs have unrecorded operating conditions and should be superseded.
To do——
Next version v2.10ComplianceCAN Bus Power Protection
D10 sourcing for production
Qualify a Littelfuse or STMicro equivalent SM8S36CA for CE / ABYC certification; the current FUXINSEMI part is suitable for prototype but not preferred for production compliance documentation.
To do——
Next version v2.10HardwareCAN Bus Power Protection
D7 substitution if loaded clamp exceeds 40 V
Swap to a lower-standoff part (e.g. PESD12VL1BA, ~34 V clamp at 200 W) if the V2.9 bench measurement shows the INA219 VS abs-max could be reached.
To do——
Next version v2.10HardwareCAN Bus Power Protection
D8 proximity
Tighten D8 to within 2 mm of Q6's gate/source (currently 3.0 mm) to reduce the gate loop area.
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Next version v2.10HardwareCAN Bus Power Protection
Over-temperature disconnect
Add a genuine thermal cutout: wire a normally-closed thermal switch (85 °C or 100 °C, e.g. Murata PKGS series) in series between R44 and GNDREF, plus a 100 kΩ pull-up from Q6's gate to its source. Place the switch adjacent to the hottest component (Q6 or L3 / L4).
To do——
Next version v2.10HardwareCAN Bus Power Protection
OVP threshold margin at temperature
At 85 °C the OVP threshold reaches 15.1 V — only 300 mV above the 14.8 V NMEA 2000 maximum charging voltage. Raise the margin by adjusting R45 / R46, or replace the divider-only comparator with a voltage-reference design for temperature-stable operation.
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Next version v2.10HardwareCAN Bus Power Protection
R33 Kelvin routing
Verify INA219 IN+ and IN− sense traces leave the inner edges of R33's pads, separate from the main VS+ power traces, to minimise current-measurement error.
To do——
Next version v2.10HardwareCAN Transceiver
C36 population decision
Resolve DNP status after EMC testing; either populate or remove the footprint.
To do——
Next version v2.10ComplianceCAN Transceiver
NMEA 2000 certification
The physical layer meets ISO 11898-2 but formal NMEA 2000 certification has not been pursued; required before any commercial release.
To do——
Next version v2.10HardwareCAN Transceiver
Tighten C18 placement
Move C18 adjacent to U5 pin 3 to reduce the bulk-bypass trace from ~5.6 mm to ≤ 3 mm.
To do——
Next version v2.10HardwareCAN Transceiver
TWAI_TX damping footprint
No series resistor is fitted on TXD. Add a DNP 0603 footprint to allow evaluation at bring-up without a board respin.
To do——
Next version v2.10HardwareCAN Transceiver
U10 clamp margin
U10 clamps at 40 V @ 5 A while the SN65HVD234DR bus-fault spec is ±36 V. Confirm U5 survives the worst-case bus fault before committing to a production run; if marginal, swap U10 for a lower-clamping CAN TVS array.
To do——
Next version v2.10HardwareDisplay Interface
C37 dielectric / voltage-derating confirmation
confirm the Murata "BZ" series code corresponds to a temperature characteristic (X5R vs Y5V / Z5U) where the effective capacitance at 5 V DC bias remains ≥ 4.7 µF. If derating is severe, swap for an X5R-rated 10 µF / 25 V 0805 part.
To do——
Next version v2.10HardwareDisplay Interface
DISP_TX / DISP_RX series damping if traces ≥ 50 mm
already tracked under `## esp32-module` in `v2.10-improvements.md`; cross-referenced from this page because the damping resistors belong adjacent to each transmitter (U3 DISP_TX pad and the display module TX pad respectively).
To do——
Next version v2.10HardwareDisplay Interface
LCSC URLs in schematic
C37, C38, and FB3 KiCAD property fields currently reference LCSC datasheet URLs. Replace with Murata manufacturer URLs in a V2.10 schematic pass.
To do——
Next version v2.10HardwareESP32 Module
DISP_TX / DISP_RX series damping
Likely longer traces than the J1 path; same 33 Ω damping policy if > 50 mm. The damping resistors belong adjacent to the *transmitter* output (U3 DISP_TX pad and the display module TX pad respectively).
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Next version v2.10HardwareESP32 Module
ESP_TX / ESP_RX trace length verification
Measure actual routed length in the KiCAD PCB editor. If either trace exceeds 50 mm, add 33 Ω series damping at the U3 output pads per the ESP-PROG Hardware Guide. (Straight-line distance is ~29.5 mm; routed length not yet extracted.)
To do——
Next version v2.10HardwareESP32 Module
Move I²C pull-up sub-circuit onto the esp32_module sheet
Relocate the I²C bus pull-ups — R1 (SCL) and R2 / R3 (SDA, parallel) — from the i2c_sensors KiCad sheet onto esp32_module.kicad_sch alongside U3, so the schematic places the pull-ups where they logically belong (with the MCU / bus master) and they appear in the ESP32 Module page's schematic view. WTI400 already places its I²C pull-ups on the ESP32 module sheet; this aligns MDD400 with that convention.
To do——
Next version v2.10HardwareLegacy Serial Interface
38400 baud TX support
Requires further reduction of C48 to ~220 pF (pulse too short for cable runs > 2–3 m) or a redesigned assist stage (constant-current source or firmware-adaptive baud-rate detection).
To do——
Next version v2.10HardwareLegacy Serial Interface
C30 dedicated bypass at U7 pin 6
Currently 3.3 mm; add a dedicated 100 nF 0603 adjacent to pin 6 if bring-up shows high-speed switching issues.
To do——
Next version v2.10HardwareLegacy Serial Interface
C48 rework on existing V2.9 boards
Change C48 from 2.2 nF to 820 pF (R59 unchanged at 12 kΩ). Same 0603 C0G footprint; update schematic value and rework all assembled units before TX bring-up.
To do——
Next version v2.10HardwareLegacy Serial Interface
C49 / C50 schematic metadata
KiCAD lists the wrong manufacturer part (GRM188R71H104KA93D, 100 nF); the correct part is GRM1885C1H101JA01D (100 pF). Assembled BOM is correct; fix the schematic property fields.
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Next version v2.10HardwareLegacy Serial Interface
Connector swap to M12 3-pin
Replace J3's proprietary Raymarine-compatible THT footprint with an M12 A-code or B-code 3-pin male panel-mount socket (IP67, field-wireable). The SeaTalk I pin assignment (power / ground / signal) maps directly. No circuit changes required.
To do——
Next version v2.10HardwareLegacy Serial Interface
D9 proximity to ST_SIG boundary
Confirm D9 is within 5 mm of the isolation boundary; relocate closer in V2.10 for better transient suppression.
To do——
Next version v2.10HardwareLegacy Serial Interface
Guard ring around U7 isolation gap
Marine salt-spray increases ionic creepage risk on uncoated boards; add an unconnected guard trace if conformal coating is not specified.
To do——
Next version v2.10HardwareLegacy Serial Interface
LDO bypass distances
Move C55 (currently 9.2 mm from U11 VIN) and C54 (currently 5.0 mm from U11 VOUT) to within 2 mm of their respective U11 pins. Confirm via DRC.
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Next version v2.10ComplianceLegacy Serial Interface
PCB creepage slot at U8 / U9
The 1.4 mm copper-free gap meets IEC 60747-5-5; a milled PCB slot increases creepage. Evaluate when CE marking or MED certification is pursued.
To do——
Next version v2.10HardwareLegacy Serial Interface
Rise-time-assist component placement
C48, Q11, R36, R40, R42, R47, R59, R61 PCB positions were not recoverable from review data; confirm placement relative to Q12 in the PCB editor.
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Next version v2.10CompliancePCB Markings & Compliance
Compliance test reports
The CE, UKCA, and FCC marks on the silkscreen indicate the device is designed for compliance with the corresponding standards. The actual *test reports* that authorise affixing those marks are part of the V2.10 compliance pre-screening campaign (CISPR 32 conducted emissions, FCC Part 15 radiated, RED 2014/53/EU harmonised standards). The marks should not be affixed on production boards until the test reports are signed off.
To do——
Next version v2.10HardwarePCB Markings & Compliance
Copyright year update
Refresh S8 to the V2.10 production year if it differs from 2025.
To do——
Next version v2.10HardwarePCB Markings & Compliance
Re-scan QR code URL
Confirm the deployed URL still matches the silkscreen QR on the V2.10 PCB before fabrication.
To do——
Next version v2.10HardwarePower Monitor
Kelvin sense connection at R33
verify in the V2.10 layout pass that IN+ / IN− tap from the *inner* edges of R33's pads (not from a downstream point), so the sense voltage is exactly V<sub>R33</sub> rather than V<sub>R33</sub> + trace drop.
To do——
Next version v2.10HardwarePower Monitor
Shorten sense-pair routing
the IN+ / IN− pair currently runs ~60 mm from R33 (in the CAN bus-power section) to U2 (in the sensor cluster). Move U2 closer to R33 or route the sense pair on an inner layer away from SMPS switching activity to tighten common-mode rejection.
To do——
Next version v2.10HardwarePower Supplies
Address dual-converter in-phase 400 kHz EMI
*(conditional on V2.9 EMC pre-scan)* — both LMR51610 instances run fixed-frequency with no phase synchronisation; in-phase coincidence sums common-mode emissions at 400 kHz and its harmonics. Options: spread-spectrum LMR variant; deliberate frequency offset via an RT-pin component on one converter (only if a frequency-trim pin is exposed on the chosen variant); a sync-capable converter with deliberate 180° phase shift; or — if EMC still passes — accept and document.
To do——
Next version v2.10HardwarePower Supplies
Concentrated thermal via array under each LMR51610 GND pin
*(conditional on V2.9 thermal soak)* — DBV/SOT-23-5 has no exposed pad; add a tight cluster directly under each IC's GND pin if margin proves tight.
To do——
Next version v2.10HardwarePower Supplies
Swap U1 / U6 to LMR51610XDRGR (DRG package, exposed pad)
*(if VCC or VDD continuous load grows, or if V2.9 thermal soak shows IC case > ~95 °C)* — DRG θJA = 48 °C/W vs DBV's 148 °C/W. ~20 °C extra Tj headroom on each rail; same improvement as the WTI400 V1.3 backlog.
To do——
Next version v2.10HardwarePower Supplies
Switch L1 / L2 from Fenghua FNR5040S220MT (prototype stock) to Bourns SRN5040TA-220M (production BOM)
same footprint; ~+0.4–0.5 % efficiency per rail and a guaranteed SRF spec.
To do——
Next version v2.10HardwareProgramming Socket
ESP_TX / ESP_RX trace-length verification
Straight-line distance is ~29.5 mm; extract actual routed length in the PCB editor. If either trace exceeds 50 mm, add 33 Ω series damping at the U3 output pads per the ESP-PROG Hardware Guide. Cross-referenced from the [ESP32 Module](./esp32-module) page.
To do——
Next version v2.10HardwareProgramming Socket
Expand U4 F.Cu pour / thermal vias
*(conditional on V2.9 thermal soak)* — If the 30-minute Wi-Fi TX soak shows Tj exceeding 110 °C at 70 °C ambient, increase the 64 mm² F.Cu pour and / or add to the 16-via thermal cluster under the tab. The HT7833 tab is V_IN (Net-(D3-K)), **not GND** — layout must not connect to GNDREF.
To do——
Next version v2.10HardwareProgramming Socket
Tighten U4 V_IN decoupling
The nearest dedicated capacitor to U4 V_IN is C22 (100 nF) at ~3.3 mm — outside the ≤ 1 mm tight-decoupling guideline. Stable at the load currents in use; add a dedicated 100 nF 0603 adjacent to U4 V_IN if any oscillation is observed during the thermal soak.
To do——
Next version v2.10HardwareTemperature Sensor
Add 100 nF X7R bypass on TMP112 V<sub>CC</sub>
in parallel with C57 (100 pF). TMP112 datasheet §9.2 recommends 100 nF minimum; the V2.9 100 pF C0G is below this guideline. At the TMP112's ~50 µA idle current the risk is low, but adding the 100 nF would follow the datasheet and reduce susceptibility to supply glitches during I²C transactions.
To do——
Click any row to expand assignee, dependencies, notes and evidence links. Click any column header to sort. A ⛓ badge next to status indicates the task has dependencies — green = all done, red = some still open.

Legend​

Kind​

  • Verification — bring-up test against the current hardware revision. Pulled from each circuit-design page's ## Testing & Verification admonition under Hardware bring-up / Conditional.
  • Next version — design / rework item targeted at a future hardware revision. The badge includes the target version (e.g. v2.10). Pulled from each circuit-design page's ## Testing & Verification admonition under For V2.10... / Before next production run....

Category​

  • Hardware — work against the assembled PCB (most of the current list).
  • Firmware — integration / regression test that needs the hardware running. (None yet in this list.)
  • Housing — IP-rating, mechanical fit, drop, vibration, environmental test. (None yet.)
  • Compliance — CISPR 32 conducted, FCC Part 15 radiated, RED 2014/53/EU harmonised standards, NMEA 2000 conformance, etc.

Status​

  • To do — not yet attempted.
  • In progress — being worked on now.
  • Done — completed with a recorded result.
  • Blocked — can't proceed (waiting on parts, equipment, or upstream dependency).
  • Deferred — intentionally postponed to a later campaign or version.
  • N/A — no longer relevant (e.g. superseded by a design change).

Dependency chain (⛓ badge)​

The ⛓ badge next to a status indicates the task has upstream dependencies. Green = all dependencies are done. Red = some dependencies are still open (the task may need to wait). Expand the row to see the dependency list with each upstream task's status inline.

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Editing workflow​

Update the JSON file alongside the task execution:

  • Change status to "in_progress" while working, then "done" when complete.
  • Fill in date_completed (ISO format, e.g. "2026-06-15") and result (free-text — e.g. "3.302 V — within spec" or "Failed at 250 mA — see notes").
  • Add notes for unexpected behaviour, observations, lessons learned.
  • Add assignee if it's a delegated task (free-text — operator or team name).
  • Add dependencies (array of upstream task IDs) if the task can't start until other items complete.
  • Add evidence URLs for scope captures, photos, or log files (relative paths to /assets/bringup/mdd400-v2.9/<task-id>.png work; external URLs also work).

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How this list is maintained​

The list is hand-maintained. It was seeded once from each circuit-design page's ## Testing & Verification :::caution admonition — the Hardware bring-up / Conditional bullets became kind: "verification" tasks; the For V2.10... / Before next production run... bullets became kind: "next-version" tasks.

When a circuit page gains a new bullet, add a matching entry to tasks.json. When a circuit page bullet is reworded, update the matching entry's description to stay in sync. The hardware-repo backlog file v2.10-improvements.md in MDD400/PCB/MDD400_V2.9/ remains the canonical narrative for next-version rationale; this page is the live state tracker.

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