Power Supplies
MDD400 v2.9 — Fabricated prototype — testing phase
Overview
The MDD400 has two regulated supplies, generated by two independent LMR51610 synchronous buck converters running from the protected bus supply (VSD ≈ 12 V, sourced from the CAN Bus Power section via FB4). They are drawn on the power_supplies KiCad sheet:
- The LMR51610 converter — the shared converter topology used by both rails (LMR51610XDBVR, 22 µH inductor, identical surrounding circuit).
- VCC 3.3 V — powers the ESP32-S3 module (U3) and all digital logic.
- VDD 5.0 V — powers the DWIN capacitive touch display (gated by a high-side switch on the Display Interface page) and the MLT-8530 buzzer.
The two converters use the same chip (LMR51610XDBVR), the same inductor footprint (Bourns SRN5040TA-220M, 22 µH), and an identical surrounding circuit topology. Only three things differ per rail: the feedback divider values that set the output voltage, the board placement, and what each rail drives. This page describes the shared converter once, then states the per-rail specifics and performance numbers separately.
The two converters sit side-by-side at the top of the schematic — VDD (U6) on the left, VCC (U1) on the right. The "Isolation of Power Domains" sub-diagram (lower-left area of the sheet) makes the ferrite strategy explicit: an input ferrite (FB4) at the CAN→SMPS boundary, plus an output ferrite per rail (FB1 for VCC, FB2 for VDD) with a 100 pF rail bypass cap right at each output ferrite pad.
The circuit topology and the four-layer GNDREF / moat / via-fence layout strategy are identical to the WTI400 V1.2 Power Supply page (/wti400/v1.2/circuit-design/power-supplies). Where this page says "follows the same pattern as WTI400", refer to that page for the per-rule MPS EMI webinar explanation; the MDD400-specific deltas (dual converters, two-cell moat, per-rail consumers, dual-converter EMI flag) are covered here.
Functional specification and design objectives
The power supplies section must:
- generate a 3.3 V rail (VCC) for the ESP32-S3 module and all digital logic, and a 5.0 V rail (VDD) for the DWIN display and buzzer, both from the ≈ 12 V protected bus supply;
- supply VCC's worst-case ~360 mA (ESP32-S3 802.11b TX plus sensors and pulls) and VDD's worst-case ~400 mA (display backlight at 100 % plus buzzer) with output capacitance covering boot / RF-ramp / inrush transients;
- hold output ripple well below the 50 mV pp target and keep both ICs within their 125 °C junction-temperature limit across the operating ambient range;
- contain SMPS switching noise within a per-converter moated cell so the two converters do not couple into each other or into the digital rails; and
- present a single high-frequency boundary (one output ferrite per rail) between each SMPS-side rail and its digital-side rail.
The LMR51610 converter — shared description
How it works
Each converter is built around an LMR51610XDBVR (TI synchronous buck, SOT-23-5 DBV, 400 kHz fixed switching frequency, integrated high-side + low-side MOSFETs). The surrounding components are functionally identical across the two instances; only the refdes and FB divider values change. The VCC converter (U1) sits on the right of the schematic above; the VDD converter (U6) on the left is a mirror with the same topology and different FB divider values.
Per-converter components (VCC instance / VDD instance):
- Input stage: 10 µF X7R 1210 bulk (C15 / C33) + 100 nF X7R 0603 HF bypass (C6 / C21) at the VIN pin. Two-tier decoupling, HF cap closest to VIN — minimises the input hot-loop area.
- Bootstrap (CB↔SW): 100 nF X7R 0603 (C10 / C25). Connects the LMR51610 CB (CBOOT) pin to the SW node; charged during off-time via the IC's internal LDO, delivers gate-drive voltage above SW during on-time.
- Feedforward (Vout↔FB across upper divider): 1 pF C0G 0603 (C7 / C23). Across the upper FB divider resistor; introduces a zero in the feedback loop for transient response. C0G dielectric is essential at 1 pF — X5R/X7R would derate catastrophically at this value.
- DNP snubber footprint (SW→GNDREF): 1 nF C0G 0603 + 22 Ω 0603 (C9 + R7 / C24 + R23). Series RC between SW and GNDREF, Do-Not-Populate by default. All four parts carry
(attr smd dnp)in the current PCB. Populated only if SW-node ringing is observed during EMC bring-up. - Output filter: 22 µH semi-shielded inductor (L1 / L2, Bourns SRN5040TA-220M, 5×5 mm, 1.62 A Isat, 1.50 A Irms, 123 mΩ DCR) flanked symmetrically by 2× 10 µF X7R 1210 bulk caps (C5 + C14 / C20 + C32).
- Rail output bypass (Vout→GNDREF, just before the output ferrite): 100 pF C0G 0603 (C13 / C31). Located between the inductor output and the boundary ferrite; extends bypass response into the tens of MHz, attenuating switching harmonics on the SMPS-side rail before they reach the ferrite.
- SMPS → digital boundary ferrite: Murata BLM31KN601SN1L 1206 (FB1 / FB2, 600 Ω @ 100 MHz, 80 mΩ DCR). The sole copper path between the SMPS-side output rail (
/SMPS DOMAIN/3v3or/SMPS DOMAIN/5v0) and the digital rail (VCC or VDD). No bypass copper across the ferrite.
The PCB layout matches the MPS EMI webinar containment pattern documented in detail on the WTI400 Power Supply page — two-tier input decoupling, SW implemented as a copper pour rather than a trace, symmetric flanking output caps, sole-ferrite-at-boundary, star convergence of GND returns at the IC GND pad, and a moat / via fence / multi-layer GNDREF strategy. The MDD400-specific layout deltas are covered in the page-level PCB Layout section below.
Inductor sourcing — production vs prototype
Production BOM specifies Bourns SRN5040TA-220M for both L1 (VCC) and L2 (VDD). The current V2.9 prototype boards are populated with Fenghua FNR5040S220MT (same footprint, stock-available substitute).
| Parameter | Bourns SRN5040TA-220M (production) | Fenghua FNR5040S220MT (prototype) | Impact |
|---|---|---|---|
| Inductance | 22 µH | 22 µH | No change |
| DCR | 123 mΩ | 168 mΩ | +45 mΩ with Fenghua — main difference |
| Saturation current Isat | 1.62 A | 1.8 A | Fenghua slightly higher; both > 3× over peak IL_peak ≈ 500–605 mA |
| RMS current Irms | 1.50 A | 1.6 A | Both well above design IL_rms ≈ 448 / 518 mA (VCC / VDD) |
| Package | 5×5 mm semi-shielded | 5×5 mm shielded | Functionally equivalent footprint |
| Self-resonant frequency | ≥ 16 MHz (datasheet) | Not listed (typical > 5 MHz for this form factor) | Both well above the 400 kHz fundamental |
At the design peak loads, the higher Fenghua DCR adds:
| Rail | Iout (design peak) | Bourns inductor loss | Fenghua inductor loss | Δ loss | Δ DC drop |
|---|---|---|---|---|---|
| VCC (3.3 V) | 360 mA | 15.9 mW | 21.8 mW | +5.9 mW | +16.2 mV |
| VDD (5.0 V) | 400 mA | 19.7 mW | 26.9 mW | +7.2 mW | +18.0 mV |
Efficiency reduction ~0.4–0.5 % per rail at the typical operating point. Junction-temperature margin on U1 / U6 is unchanged (the extra few mW dissipates in the inductor, not the IC). Saturation margin is actually slightly better with Fenghua because its Isat rating is higher. The reason for the production switch to Bourns is the lower DCR (better efficiency) and the guaranteed SRF spec — not a fitness-for-purpose concern with Fenghua.
VCC 3.3 V — for the ESP32 module
How it works
Feedback divider
- Upper: R6 = 100 kΩ (3v3 → FB pin)
- Lower: R5 = 32 kΩ (FB pin → GNDREF)
V_out = V_ref × (1 + R6/R5) = 0.8 × (1 + 100 kΩ / 32 kΩ) = 3.300 V
Consumers
The dominant VCC consumer is U3 — ESP32-S3-WROOM-1-N16R8. Per the Espressif ESP32-S3 datasheet (Table 16, "Current consumption in active mode"):
- 802.11b TX at 11 Mbps, P_OUT = +18 dBm: 350 mA typical
- 802.11g TX at 54 Mbps, P_OUT = +15 dBm: 280 mA typical
- 802.11n TX at MCS7, P_OUT = +13 dBm: 240 mA typical
- RX, listening: 95 mA
- Modem-sleep: 25 mA
The worst single-mode continuous draw is 802.11b TX at 350 mA. Adding the other VCC consumers:
| Consumer | Worst-case current | Notes |
|---|---|---|
| U3 — ESP32-S3 Wi-Fi 802.11b TX | 350 mA | Datasheet typical, +18 dBm |
| I²C sensors (BME280 + LSM6DSL on the I²C bus) | < 5 mA combined | Normal mode |
| Display interface signals (UART2 TX/RX, DISP_EN driving Q5/Q4) | < 1 mA | Logic-level only; VDSP itself is on VDD |
| Pull-ups (R4 EN, R24 IO0, button/LED pulls) | < 2 mA | Worst-case all asserted low |
| Other (filter quiescent, leakages) | < 5 mA | Margin |
| VCC design peak (rounded up) | ~360 mA | Rail headroom design point |
This figure is conservative for sustained operation. Boot, RF ramp, and ESP-PROG load transients can briefly exceed it; output capacitance handles those.
Developer / kit variant note: In the developer variant, U4 (HT7833 LDO on the ESP32 Module page) supplies VCC from VDD as a back-up path that protects the ESP32 if the ESP-PROG programmer is fed 5 V at the IDC connector. In production U4 is DNP and R22 (0 Ω link) replaces it — VCC feeds U3 directly from this SMPS. The SMPS budget above is what counts in either case.
Performance
| Parameter | Value | Condition | Notes |
|---|---|---|---|
| Output voltage | 3.300 V | Calculated from R5/R6 | Exactly on target |
| Switching frequency | 400 kHz | Fixed (datasheet) | — |
| Duty cycle | 27.5 % / 18.3 % | V_in = 12.0 V / 18.0 V | CCM, ideal |
| Inductor ripple ΔIL | 272 mA / 306 mA | V_in = 12.0 V / 18.0 V | Healthy CCM |
| Peak inductor current IL_peak | 496 mA / 513 mA | 360 mA load | 32 % of Isat 1.62 A — 68 % margin |
| Inductor RMS current | ~448 mA | Iout + ΔIL/(2√3) | 30 % of 1.5 A Irms rating |
| Estimated output ripple | ~4–7 mV pp | C_eff = 20 µF, ΔIL = 272 mA | Well below 50 mV target |
| IC dissipation estimate | ~180–200 mW | Scaled from WEBENCH 110 mW @ 240 mA | — |
| Junction temp rise | ~28 °C | θJA = 148 °C/W (DBV/SOT-23-5) | At 190 mW Pdiss |
| Tj at 85 °C ambient | ~113 °C | Worst credible thermal case | 12 °C margin below 125 °C limit |
Margin is tighter than the original WEBENCH report indicated because the design load has been updated from 240 mA (WEBENCH) → 360 mA (ESP32-S3 datasheet). The DRG-package swap (see Gaps & next version) restores generous headroom if needed.
VDD 5.0 V — for the display and buzzer
How it works
Feedback divider
- Upper: R19 = 100 kΩ (5v0 → FB pin)
- Lower: R18 = 19.1 kΩ (FB pin → GNDREF, 0.1 % thin-film)
V_out = V_ref × (1 + R19/R18) = 0.8 × (1 + 100 kΩ / 19.1 kΩ) = 4.989 V ≈ 5.0 V
Consumers
| Consumer | Worst-case current | Notes |
|---|---|---|
| DWIN DMG48480F040_01WTC display (via VDSP) | ~250–350 mA | 4.0 " IPS 480×480 + capacitive touch; backlight PWM dominates; gated by Q4 on the Display Interface page |
| MLT-8530 buzzer (during sound) | ~30 mA | Magnetic SMD buzzer; only drawn during alarm/notification |
| Filter quiescent, leakages | < 5 mA | — |
| VDD design peak (rounded up) | ~400 mA | Display backlight at 100 % + buzzer simultaneously |
The VDD design load is dominated by the DWIN backlight at full brightness. Firmware typically PWM-dims the backlight (lower average current), but the rail must handle 100 % brightness continuously for outdoor / direct-sunlight operation. The buzzer is a brief transient; output capacitance handles the turn-on inrush.
Performance
| Parameter | Value | Condition | Notes |
|---|---|---|---|
| Output voltage | 4.989 V ≈ 5.0 V | Calculated from R18/R19 | Within LMR51610 reference accuracy |
| Switching frequency | 400 kHz | Fixed (datasheet) | Same as VCC — see EMI flag below |
| Duty cycle | 41.7 % / 27.8 % | V_in = 12.0 V / 18.0 V | CCM, ideal |
| Inductor ripple ΔIL | 331 mA / 410 mA | V_in = 12.0 V / 18.0 V | Higher than VCC because V_out is higher |
| Peak inductor current IL_peak | 566 mA / 605 mA | 400 mA load | 37 % of Isat 1.62 A — 63 % margin |
| Inductor RMS current | ~518 mA | Iout + ΔIL/(2√3) | 35 % of 1.5 A Irms rating |
| Estimated output ripple | ~5–8 mV pp | C_eff = 20 µF, ΔIL = 331 mA | Well below 50 mV target |
| IC dissipation estimate | ~190–220 mW | Scaled from WEBENCH 90 mW @ 240 mA | — |
| Junction temp rise | ~30 °C | θJA = 148 °C/W (DBV/SOT-23-5) | At 200 mW Pdiss |
| Tj at 85 °C ambient | ~115 °C | Worst credible thermal case | 10 °C margin below 125 °C limit |
Same DRG-package consideration as VCC — V2.10 swap restores headroom.
PCB Layout
The MDD400 power supplies section follows the same MPS EMI webinar containment pattern as WTI400, but applied per-converter: each LMR51610 instance sits inside its own moat-bounded cell on F.Cu / In1.Cu / In2.Cu, with an outer moat enclosing both cells. The four-layer GNDREF role assignment is the same as WTI400 — refer there for the per-rule explanation.
- Two independent moated cells + outer moat. Each converter has its own moat-bounded cell (VCC/U1 top, VDD/U6 below). The moats are 0.4 mm
copper pour not allowedkeepouts cut on F.Cu, In1.Cu, and In2.Cu, with a perimeter via fence stitching the inside-moat GNDREF down to the continuous B.Cu plane. The two cells share an inter-cell moat segment; neither cell's GNDREF copper connects to the other on layers 1–3 except through the B.Cu plane below. An outer moat encloses both cells, separating the SMPS area from the rest of the board. 195 GNDREF stitching vias (0.3 mm drill) connect F.Cu to In1.Cu and In2.Cu in the SMPS area. Isolating the two converters from each other (not just from the rest of the board) is what differs from WTI400's single-cell layout. - B.Cu spans the full board uninterrupted (no moat) — the global GNDREF reference that ties everything together at low impedance.
- Per-converter placement (connector-first signal order). Each converter is a 180°-mirrored clone on a vertical column at x ≈ 79.5 mm: the HF input cap (C6/C21) sits ~2.6 mm from VIN and the 10 µF bulk input cap (C15/C33) ~7 mm out; the bootstrap cap (C10/C25) ~2.6 mm from CB/SW; the SW node is a copper pour (not a trace) carrying it directly to the inductor (L1/L2); the output bulk caps (C5/C14, C20/C32) bracket the inductor output; the feedforward cap and FB divider (C7/R5/R6, C23/R18/R19) sit within ~3 mm of the FB pin; and the rail bypass cap (C13/C31) sits 1.4 mm before the output ferrite. The feedback GND return and the VIN-cap GND return converge on the inner GNDREF planes (LMR51610 §8.4.1.2), not on a distant top-layer via.
- VCC plane pair in the digital area. The digital VCC area uses a VCC plane pair — F.Cu and B.Cu carry VCC pour while In1.Cu and In2.Cu carry unbroken GNDREF — so each VCC↔GNDREF plane pair acts as distributed bypass capacitance. A similar VDD plane-pair region appears wherever VDD distribution copper runs on F.Cu/B.Cu over inner-layer GNDREF.
- Inter-rail boundary ferrites. FB1 (3v3 → VCC) and FB2 (5v0 → VDD) sit at the right-hand boundary (x = 89 mm) of their cells; each is the sole copper bridge between its SMPS-side rail and digital-side rail, with no bypass copper crossing the bead. FB4 (VSC → VSD) at the south end is the CAN-power input filter feeding both converters (covered on the CAN Bus Power page).
- The snubber footprints (C9/R7, C24/R23) are placed at the SW-pour edge and all four carry
(attr smd dnp)in the current PCB — reachable for post-EMC population without rework. Output bulk caps bracket the inductor output along one axis (C14/C32 at 4.1 mm, C5/C20 at 8.2 mm) rather than being symmetrically distributed on both sides.
 |  |
| F.Cu — two cells inside outer moat | In1.Cu — per-cell GNDREF + via fence |
 |  |
| In2.Cu — per-cell GNDREF + via fence | B.Cu — full-board GNDREF, no moat |
The schematic carries an "Isolation of Power Domains" sub-diagram that lays out the ferrite strategy on a single picture: one input ferrite (FB4) at the CAN→SMPS boundary, then one output ferrite per SMPS rail (FB1 for VCC, FB2 for VDD), each with its 100 pF rail bypass cap (C13 / C31) right at the ferrite pad.
Components
| Ref | Value | Function | Datasheet |
|---|---|---|---|
| U1 | LMR51610XDBVR | Synchronous buck converter, SOT-23-5, 400 kHz — VCC 3.3 V | TI LMR51610 |
| U6 | LMR51610XDBVR | Synchronous buck converter, SOT-23-5, 400 kHz — VDD 5.0 V | TI LMR51610 |
| L1 | 22 µH semi-shielded inductor, 5×5 mm | Production: Bourns SRN5040TA-220M (Isat 1.62 A, Irms 1.50 A, DCR 123 mΩ). Prototype (stock substitute): Fenghua FNR5040S220MT (Isat 1.8 A, Irms 1.6 A, DCR 168 mΩ). See Inductor sourcing. — VCC output filter | Bourns SRN5040TA · Fenghua FNR5040 (LCSC) |
| L2 | 22 µH semi-shielded inductor, 5×5 mm | Production: Bourns SRN5040TA-220M (Isat 1.62 A, Irms 1.50 A, DCR 123 mΩ). Prototype (stock substitute): Fenghua FNR5040S220MT (Isat 1.8 A, Irms 1.6 A, DCR 168 mΩ). See Inductor sourcing. — VDD output filter | Bourns SRN5040TA · Fenghua FNR5040 (LCSC) |
| FB1 | BLM31KN601SN1L | 1206 ferrite bead, 600 Ω @ 100 MHz, 80 mΩ DCR — sole 3v3 → VCC copper path | Murata BLM31KN601SN1L |
| FB2 | BLM31KN601SN1L | 1206 ferrite bead, 600 Ω @ 100 MHz, 80 mΩ DCR — sole 5v0 → VDD copper path | Murata BLM31KN601SN1L |
| FB4 | BLM31KN601SN1L | 1206 ferrite bead — VSC → VSD CAN-domain input filter (covered on the CAN Bus Power page) | Murata BLM31KN601SN1L |
| C15 | 10 µF / 50 V X7R 1210 | VCC converter VSD input bulk capacitor | Murata GRM32ER71H106KA12L |
| C33 | 10 µF / 50 V X7R 1210 | VDD converter VSD input bulk capacitor | Murata GRM32ER71H106KA12L |
| C6 | 100 nF / 50 V X7R 0603 | VCC converter VIN high-frequency bypass | Murata GRM188R71H104KA93D |
| C21 | 100 nF / 50 V X7R 0603 | VDD converter VIN high-frequency bypass | Murata GRM188R71H104KA93D |
| C10 | 100 nF / 50 V X7R 0603 | VCC bootstrap capacitor — CB↔SW (charges high-side gate driver) | Murata GRM188R71H104KA93D |
| C25 | 100 nF / 50 V X7R 0603 | VDD bootstrap capacitor — CB↔SW | Murata GRM188R71H104KA93D |
| C7 | 1 pF / 100 V C0G 0603 | VCC feedforward capacitor — across R6 (3v3 → FB), sets a feedback zero | Murata GCM1885C2A1R0BA16D |
| C23 | 1 pF / 100 V C0G 0603 | VDD feedforward capacitor — across R19 (5v0 → FB) | Murata GCM1885C2A1R0BA16D |
| C9 | 1 nF / 50 V C0G 0603 | VCC SW-node snubber capacitor — DNP; fit only if SW ringing observed | — |
| C24 | 1 nF / 50 V C0G 0603 | VDD SW-node snubber capacitor — DNP | — |
| C5 | 10 µF / 50 V X7R 1210 | VCC output bulk capacitor — flanks L1 | Murata GRM32ER71H106KA12L |
| C14 | 10 µF / 50 V X7R 1210 | VCC output bulk capacitor — flanks L1 (symmetric with C5) | Murata GRM32ER71H106KA12L |
| C20 | 10 µF / 50 V X7R 1210 | VDD output bulk capacitor — flanks L2 | Murata GRM32ER71H106KA12L |
| C32 | 10 µF / 50 V X7R 1210 | VDD output bulk capacitor — flanks L2 (symmetric with C20) | Murata GRM32ER71H106KA12L |
| C13 | 100 pF / 50 V C0G 0603 | VCC rail output bypass — 3v3 → GNDREF just before FB1 | — |
| C31 | 100 pF / 50 V C0G 0603 | VDD rail output bypass — 5v0 → GNDREF just before FB2 | — |
| R5 | 32 kΩ 0603 thin film ±0.1 % | VCC feedback divider lower (sets 3.30 V with R6) | Yageo RC Group |
| R6 | 100 kΩ 0603 thick film ±1 % | VCC feedback divider upper (3v3 → FB) | Yageo RC Group |
| R7 | 22 Ω 0603 thick film ±1 % | VCC SW-node snubber resistor (with C9) — DNP | Yageo RC Group |
| R18 | 19.1 kΩ 0603 thin film ±0.1 % | VDD feedback divider lower (sets 4.99 V with R19) | Yageo RC Group |
| R19 | 100 kΩ 0603 thick film ±1 % | VDD feedback divider upper (5v0 → FB) | Yageo RC Group |
| R23 | 22 Ω 0603 thick film ±1 % | VDD SW-node snubber resistor (with C24) — DNP | Yageo RC Group |
| TP1 | — | GNDREF test point — DNP | — |
Testing & Verification
V2.9 is a fabricated prototype in the bench-test phase. Both LMR51610 converters power up and deliver their rails — the ESP32 boots from VCC and the DWIN display runs from VDD on the prototype. No quantitative bench measurements have been performed on output ripple, switch-node ringing, IC thermal soak, or the dual-converter EMI signature yet. The dual-converter common-mode EMI scan is the most important new measurement for MDD400 because both LMR51610 instances run at the same fixed 400 kHz with no phase relationship.
Hardware bring-up (rig at the bench):
- Output-voltage accuracy — Probe VCC at TP1 and VDD at the inductor-side of FB2 with no Wi-Fi or display activity. Pass if 3.30 V ± 2 % (VCC) and 5.00 V ± 2 % (VDD).
- Output ripple at full load — 100 MHz scope with ≤ 5 mm-tip ground. For VCC sustain an 802.11b TX burst; for VDD set DWIN backlight to 100 %. Pass if < 50 mV pp at 400 kHz on both rails.
- IC case temperature soak — 10 min worst-case load at 85 °C enclosure ambient (or scaled). Touch-probe U1 and U6. Pass if case < ~95 °C (Tj < ~115 °C). Hotter readings are a strong DRG-package-swap signal.
- Snubber decision — 500 MHz scope on each SW node with low-inductance ground spring; capture rising edge. Pass without snubber if peak ringing < ~1 V above V_in; otherwise populate R7+C9 (VCC) or R23+C24 (VDD).
- Dual-converter common-mode EMI pre-scan — Capture conducted-emission spectrum on the VSD input with both converters running. Pass if 400 kHz / 800 kHz / 1.2 MHz peaks stay below the EMC margin; peaks above margin motivate the V2.10 phase-staggering work.
Gaps & next version
Before next production run
- Switch L1 and L2 from Fenghua FNR5040S220MT (prototype stock) to Bourns SRN5040TA-220M (production BOM) — same footprint; ~+0.4–0.5 % efficiency per rail at the design loads and a guaranteed SRF spec. See Inductor sourcing for the full analysis.
Next version (V2.10)
- Address dual-converter in-phase 400 kHz EMI (conditional on V2.9 EMC pre-scan) — V2.9 runs both LMR51610 instances at fixed 400 kHz with no phase synchronisation. When in-phase by chance, common-mode emissions sum at 400 kHz and its harmonics. This was not addressed in V2.9. Options: spread-spectrum LMR variant if available; deliberate frequency offset via an RT-pin component on one converter (only if a frequency-trim pin is exposed on the chosen variant); a sync-capable converter with deliberate 180° phase shift; or — if EMC still passes — accept and document.
- Switch U1 and U6 to LMR51610XDRGR (DRG package, exposed pad) (if VCC or VDD continuous load grows, or if V2.9 thermal soak shows IC case > ~95 °C) — DRG θJA = 48 °C/W vs DBV's 148 °C/W. At ~190 mW (VCC) / ~200 mW (VDD) dissipation this gives ΔTj ≈ 9–10 °C vs 28–30 °C — about 20 °C of extra Tj headroom on each rail. Same improvement the WTI400 V1.3 backlog carries for its single converter.
- Concentrated thermal via array under each LMR51610 GND pin (conditional on V2.9 thermal soak) — DBV/SOT-23-5 has no exposed pad; heat flows through the GND pin. V2.9 has GNDREF copper + abundant stitching vias in the SMPS region but no concentrated cluster directly under each IC's GND pin. Add if V2.9 soak shows tighter margin than expected.
References
- Texas Instruments, LMR516xx SIMPLE SWITCHER® Power Converter, 4 V to 65 V, 0.6 A / 1 A Buck Converter Datasheet — see §8.4 for layout guidance.
- Texas Instruments, Controlling switch-node ringing in synchronous buck converters (SLYT465) — snubber design guidance.
- Texas Instruments, Design Consideration on Boot Resistor in Buck Converter (SNVAA73).
- Bourns, SRN5040TA-220M Semi-shielded AEC-Q200 Compliant Power Inductors Datasheet.
- Murata Electronics, BLM31KN601SN1L Ferrite Bead Datasheet.
- Espressif Systems, ESP32-S3 Datasheet — Table 16, current consumption in active mode.
- Espressif Systems, ESP32-S3-WROOM-1 & WROOM-1U Module Datasheet.
- DWIN, DMG48480F040_01WTC 4.0" Capacitive Touch Display — backlight + interface current consumption (verify against the production datasheet during bring-up).
- Monolithic Power Systems, EMI Webinar: Practical Grounding and Layout — the layout reference for this design.
- WTI400 V1.2 Power Supply page — the per-rule MPS EMI webinar match is documented there in detail; the MDD400 layout follows the same pattern with the dual-cell deltas noted above.
Related pages
- CAN Bus Power — derives the protected VSD bus supply (via FB4) that feeds both converter inputs
- ESP32-S3 Module — the VCC consumer (U3) and the developer-variant U4/R22 back-up path
- Display Interface — the VDD high-side switch (Q4) gating the DWIN display backlight load
- Power Rails — the VCC / VDD / VSD rail reference table for the whole board