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CAN Transceiver

CAN transceiver — full sheet
Hardware version

MDD400 v2.9 — Fabricated prototype — testing phase

Overview​

The CAN transceiver connects the MDD400 to an NMEA 2000 network. It implements the ISO 11898-2 physical layer using a TI SN65HVD234DR 3.3 V transceiver driven directly by the ESP32-S3 TWAI peripheral. An NUP2105LT1G TVS and TDK ACT45B common-mode choke sit between the Micro-C connector and the transceiver, protecting against bus transients and conducted EMI before they reach the silicon.

This page covers a single sub-circuit — the CAN Transceiver — drawn on the can_transceiver KiCad sheet.

Functional specification and design objectives​

The CAN transceiver circuit must:

  • connect the ESP32-S3 TWAI peripheral to an NMEA 2000 backbone via a DeviceNet Micro-C connector;
  • protect the transceiver from ESD and bus transients at the connector entry point;
  • suppress common-mode EMI on the bus lines before they reach the transceiver;
  • limit bus edge slew rate to reduce radiated emissions at NMEA 2000's 250 kbps operating speed;
  • hold the bus recessive during boot, before firmware has initialised the TWAI peripheral; and
  • keep the transceiver in standby until firmware explicitly enables it.

CAN Transceiver​

How it works​

NMEA 2000 physical layer​

NMEA 2000 uses the CAN physical layer defined by ISO 11898-2: a differential bus with two signals — CANH and CANL — terminated at 120 Ω at each end of the backbone. The bus operates at 250 kbps. The MDD400 connects as a drop node; network termination is provided by the backbone, not this circuit.

The ESP32-S3 implements CAN via its TWAI (Two-Wire Automotive Interface) peripheral, which presents three signals to the hardware: TWAI_TX (transmit data), TWAI_RX (receive data), and TWAI_EN (transceiver enable). TWAI_TX and TWAI_RX are assigned to GPIO13 and GPIO12 respectively — neither is an ESP32-S3 strapping pin, ensuring predictable CAN behaviour across all boot modes.

NMEA 2000 connector (J2)​

NMEA 2000 Connector and Shield block — J2 Micro-C panel-mount socket, shield handling. Zoom out to see the full sheet.

J2 is an M12 A-coded 5-pin male panel-mount socket (NMEA 2000 Micro-C) rated IP67. Full pin assignments are in the External Connectors reference. The shield pin is left floating inside the device, consistent with NMEA 2000 practice of connecting the drain wire to vessel ground at a single external point only.

NMEA 2000 M12 A-coded male connector — front view: pin 1 Shield, pin 2 NET-S (+V), pin 3 NET-C (−V), pin 4 NET-H (CAN-H), pin 5 NET-L (CAN-L)

EMC protection chain​

CAN Filter and ESD Protection block — U10 TVS, FL1 common-mode choke, C27/C28/C34/C35 filter caps. Zoom out to see the full sheet.

The signal path from J2 to U5 follows the connector-first TVS topology described in TI application note SLLA271: Connector → TVS → CMC → Transceiver. Placing the TVS before the CMC clamps high-speed transients at the connector entry point; the CMC's series impedance then limits current in the TVS shunt path during surge events.

U10 (NUP2105LT1G) is a dual-line TVS array in SOT-23, placed 11.9 mm from J2 — the closest component to the connector. It clamps both NET-H and NET-L against ESD and surge transients with a 24 V standoff voltage and 350 W peak dissipation rating. C35 and C34 (15 pF, C0G, 100 V), between U10 and FL1, shunt residual high-frequency common-mode noise from each line to GNDREF. C36 (100 pF, differential, between NET-H and NET-L) is a DNP footprint — differential capacitance can degrade signal integrity on a high-speed bus and is only populated if EMC testing reveals a specific need.

FL1 (ACT45B-510-2P-TL003) is a TDK AEC-Q200 qualified common-mode choke presenting 2800 Ω common-mode impedance at 10 MHz. It passes differential CAN signals with low insertion loss while suppressing common-mode conducted noise. C28 and C27 (15 pF each) form a second common-mode filter stage on the transceiver side of FL1, providing additional attenuation before the signal reaches U5.

No galvanic isolation

The CAN transceiver ground (GNDREF) connects directly to NET-C — the NMEA 2000 bus ground. This is intentional. The MDD400 is bus-powered from NET-S and NET-C, so GNDREF and bus ground are the same node. A galvanic isolation barrier would serve no purpose and cannot prevent ground loops that do not exist in this topology.

Isolation was evaluated in an earlier revision. The isolated DC-DC converter required to power the secondary side introduced more conducted EMI than the isolation removed, and added a switching converter and transformer to the BOM. The non-isolated topology in V2.9 is simpler, quieter, and fully adequate for a bus-powered node. The legacy serial interface is isolated for a different reason: it has a separate power supply and ground reference, which does create ground loop risk.

CAN transceiver (U5)​

CAN Transceiver block — U5 SN65HVD234DR transceiver, R16/R17/R20/R21 configuration resistors. Zoom out to see the full sheet.

U5 is a Texas Instruments SN65HVD234DR — a 3.3 V CAN transceiver in SOIC-8, compliant with ISO 11898-2 and rated to 1 Mbps. It translates between the differential CANH/CANL bus and the single-ended TWAI_TX/TWAI_RX logic signals for the ESP32-S3.

Four resistors configure U5's behaviour:

R17 (10 kΩ, TXD pull-up to VCC) holds U5's D input HIGH during boot, before the TWAI peripheral has initialised. TXD HIGH is the recessive bus state. Without R17, a floating TXD pin during reset could drive the bus dominant and block all network traffic.

R20 (10 kΩ, EN pull-down to GNDREF) holds U5's EN pin LOW at power-up. EN LOW places the SN65HVD234DR in standby; EN HIGH enables normal operation. The pull-down keeps the transceiver off the bus until firmware drives TWAI_EN HIGH.

R21 (10 kΩ, slope control) connects U5's Rs pin to GNDREF, selecting slope-control mode. This limits the bus driver edge slew rate, reducing radiated EMI. At NMEA 2000's 250 kbps, the resulting transition time (~50–100 ns) is less than 2.5% of the 4 µs bit period — negligible impact on signal integrity.

R16 (47 Ω, RXD damping) sits in series between U5's R output and TWAI_RX at the ESP32-S3 GPIO. It damps ringing caused by the GPIO input capacitance and trace inductance, preventing false bit edges from reaching the TWAI peripheral. No equivalent resistor is fitted on TXD: the transceiver's TXD input is low-impedance, and bus edge rate is governed by R21 rather than the ESP32-S3 drive strength.

V2.9 — non-isolated topology

V2.9 replaced an isolated CAN transceiver (ISO1042) with the SN65HVD234DR and removed the isolation transformer. All references to an isolated CAN interface in earlier design documents apply to previous revisions only.

VCC decoupling​

Vcc Supply Decoupling block — C18 bulk + C19 HF bypass at U5 VCC pin. Zoom out to see the full sheet.

U5's VCC (pin 3) is decoupled by C19 (100 nF, X7R, placed immediately adjacent to U5) and C18 (10 µF, X7R, bulk bypass), following the SN65HVD234 datasheet recommendation. In V2.9, C18 centre-to-centre distance from U5 is ~5.6 mm — flagged for tightening in V2.10.

Performance​

ParameterCalculationResult
Pre-CMC cap CM impedance @ 10 MHz (15 pF)1 / (2π × 10 MHz × 15 pF)1,061 Ω per line
CM attenuation per stage @ 10 MHzZ_C / (Z_FL1 + Z_C) = 1,061 / (2,800 + 1,061)−11.2 dB
Two-stage CM attenuation @ 10 MHzTwo stages combined> −22.4 dB
C36 differential filter f−3dB (100 pF, DNP, 60 Ω source)1 / (2π × 60 Ω × 100 pF)26.5 MHz — no impact on 250 kbps signal if populated
FL1 winding current (120 Ω bus termination, 1.5 V dominant)1.5 V / 120 Ω12.5 mA (rated 200 mA — 93% margin)
Bus edge rise time at Rs = 10 kΩSN65HVD234 datasheet Fig. 3950–100 ns = 1.25–2.5% of 4 µs bit period
RXD filter f−3dB (R16 = 47 Ω, C_GPIO ≈ 5 pF)1 / (2π × 47 Ω × 5 pF)677 MHz — no impact on CAN signal
U10 junction capacitance per node30 pF × 2 lines60 pF (ISO 11898-2 node budget: 100 pF) ✓
U10 clamp voltage vs. U5 bus fault spec40 V @ 5 A vs. ±36 V⚠ 4 V excess — verify survivability at bring-up

Firmware notes​

TWAI peripheral configuration​

Configure the TWAI peripheral before asserting TWAI_EN. Enabling the transceiver before initialisation is complete risks transmitting a spurious dominant bit onto a live network.

ParameterValue
Bit rate250 kbps
ModeNormal
GPIO assignmentssee Pin Assignments — assert TWAI_EN HIGH after TWAI init

NMEA 2000 uses 11-bit (standard frame) CAN identifiers. Configure the TWAI acceptance filter to receive all IDs, or filter to the specific PGNs the application requires.

NMEA 2000 PGN layer​

The CAN physical layer is the scope of this page. PGN encoding, fast-packet reassembly, and ISO 11783-3 network address claiming are handled at a higher layer and are not covered here.

PCB Layout​

The protection and filter chain is laid out connector-first, in the same order as the signal flows: J2 → U10 → C36 → C34/C35 → FL1 → C27/C28 → U5. All protection and filter components sit within 12–20 mm of J2, with U10 (the TVS) closest at 11.9 mm — clamping transients at the connector entry point per TI SLLA271.

  • Differential symmetry. C34/C35 (pre-CMC) and C27/C28 (post-CMC) are placed symmetrically about the NET-H/NET-L centreline (±2.8 mm), with FL1 centred on the same axis. NET-H and NET-L are routed at ≥ 0.2 mm width and length-matched through the filter section, so common-mode interference is not converted into differential-mode signal error.
  • Ground. A solid GNDREF plane runs under the entire circuit on both copper layers. NET-C (J2 pin 3) is bonded directly to GNDREF — the standard non-isolated NMEA 2000 node topology. U10's GNDREF return needs a short, low-inductance via adjacent to the SOT-23 pad so ESD transients are shunted before they reach the silicon.
  • Decoupling. C19 (100 nF) sits adjacent to U5's VCC pin; C18 (10 µF bulk) is ~5.6 mm centre-to-centre from U5 — above the 3 mm datasheet guideline and flagged for tightening in V2.10. R16 (47 Ω) is placed at U5's RXD output side, not the MCU side, to terminate the transceiver's output capacitance at the source.

Components​

RefValueFunctionDatasheet
J2DeviceNet Micro-C A-code maleIP67 panel-mount socket — NMEA 2000 network connectionSTA M12 Series
U10NUP2105LT1GDual-line CAN TVS array, SOT-23 — ESD and surge clamponsemi NUP2105LT1G
FL1ACT45B-510-2P-TL003Common-mode choke, AEC-Q200, 51 µH / 2800 Ω @ 10 MHzTDK ACT45B
C34, C3515 pF / 100 VC0G 0603 — pre-CMC common-mode filter capsMurata GCM1885C2A150JA16D
C27, C2815 pF / 100 VC0G 0603 — post-CMC common-mode filter capsMurata GCM1885C2A150JA16D
C36100 pF / 50 VC0G 0603 — differential filter cap across NET-H/NET-L. DNPMurata GRM1885C1H101JA01D
U5SN65HVD234DR3.3 V CAN transceiver, ISO 11898-2, SOIC-8TI SN65HVD234 (SLLS557H)
C19100 nF / 50 VX7R 0603 — U5 VCC high-frequency bypass (adjacent)Murata GRM188R71H104KA93D
C1810 µF / 25 VX5R 0805 — U5 VCC bulk bypass—
R1647 Ω0603 — RXD series damping (U5 pin 4 to TWAI_RX)—
R1710 kΩ0603 — TXD pull-up to VCC; holds bus recessive at boot—
R2010 kΩ0603 — EN pull-down to GNDREF; holds transceiver in standby at boot—
R2110 kΩ0603 — Rs slope-control resistor (U5 pin 8 to GNDREF)—

Testing & Verification​

caution

V2.9 is a fabricated prototype in the bench-test phase. The CAN transceiver section uses the non-isolated SN65HVD234DR (replacing an earlier ISO1042 with isolation transformer). TWAI loopback, live-network receive/transmit, U10 clamp survivability, and the bus-fault margin between U10's 40 V clamp and U5's ±36 V bus-fault spec have not yet been measured on the V2.9 prototype.

Hardware bring-up (rig at the bench):

  • Bus idle — recessive state — With TWAI_EN LOW, measure CANH and CANL at J2. Pass if both sit at approximately 2.5 V.
  • Transceiver enable — Assert TWAI_EN HIGH. Pass if U5 enters normal mode with no bus disturbance on a scope.
  • TXD default — Before TWAI initialised, measure TXD at U5 pin 1. Pass if HIGH (R17 holding recessive).
  • TWAI loopback — Configure the TWAI peripheral in self-test/loopback mode; transmit a frame. Pass if received without error.
  • Receive on live network — Connect to an NMEA 2000 network; capture traffic with a CAN analyser. Pass if frames are received at 250 kbps with no error frames.
  • Transmit on live network — Send a test PGN. Pass if the frame appears on the network and is acknowledged by another node.
  • Bus fault survivability — Apply a brief over-voltage to CANH / CANL at J2; confirm U10 clamps and U5 survives. Note the 4 V clamp-vs-spec margin.

Gaps & next version​

Before next production run

  • U10 clamp margin — U10 clamps at 40 V @ 5 A while the SN65HVD234DR bus-fault spec is ±36 V. U5 relies on its internal clamping structures above 36 V. Confirm U5 survives the worst-case bus fault before committing to a production run; if marginal, swap U10 for a lower-clamping CAN TVS array.
  • U10 ground via quality — A short, low-inductance via adjacent to U10 pin 3 is critical for ESD clamping effectiveness. Verify in Gerber review.

Next version (V2.10)

  • TWAI_TX damping footprint — No series resistor is fitted on TXD. Add a DNP 0603 footprint to allow evaluation at bring-up without a board respin.
  • C36 population decision — Resolve DNP status after EMC testing; either populate or remove the footprint.
  • Tighten C18 placement — Move C18 adjacent to U5 pin 3 to reduce the bulk-bypass trace from ~5.6 mm to ≤ 3 mm, per the SN65HVD234 datasheet.
  • NET-H/NET-L length match — A segment-count difference between the two traces warrants a trace-length measurement in the layout tool to confirm the ±0.5 mm match.
  • NMEA 2000 certification — The physical layer meets ISO 11898-2, but formal NMEA 2000 certification has not been pursued. Required before any commercial release.

References​