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Circuit Design

Hardware version

MDD400 v2.9 — Fabricated prototype, bench-test phase. The board has been driven end-to-end on the bench using hardware test routines: power-up, CAN/NMEA 2000 connectivity, the DWIN DGUS II display, the three I²C sensors, and the buzzer all individually functional. No production firmware has been written for V2.9 yet — the production ESP-IDF firmware is the next major project task and is planned to migrate the operational code paths (tone library, alert taxonomy, brightness-control loop, three-tier thermal protection, NMEA 2000 PGN handling) from the MDD400 V1.0 PlatformIO/Arduino predecessor, which ran on earlier MDD400 hardware revisions through significant in-service operating hours including extended open-ocean passages. Wi-Fi has never been enabled on any MDD400 board; BLE has only been exercised during early BLE-library development on test hardware. V2.9 introduces a new housing, a new ambient-light-sensor placement, and a few hardware updates from the prior revision — see each per-circuit page for the specific bring-up tasks that remain open.

Overview​

The MDD400 is a marine multi-function display node for NMEA 2000 vessel networks. It draws power and data from a single NMEA 2000 DeviceNet Micro-C connector and presents the network data — engine, navigation, environmental, alarm — on a 4.0-inch capacitive-touch DWIN display housed at the helm. It is a fully self-contained NMEA 2000 device: no external power, no auxiliary cabling, no separate display module. An optional galvanically-isolated legacy serial interface adds a backwards-compatibility path for older instrumentation (single-wire 12 V protocols and NMEA 0183).

This page narrates the system at the board level — the block diagram, power and signal flow, the four electrical isolation domains, the PCB stack-up, and the EMC philosophy that ties the layout together. Each functional block links to its own page where the schematic, layout, performance review, and firmware integration are documented in detail.

MDD400 V2.9 hierarchical block diagram — the parent KiCad sheet showing each sub-sheet as a labelled block, with the inter-sheet bus connections (VDD, VCC, GNDREF, TWAI bus, I²C bus, DISP_* bus, ST_* bus, etc.) routed between blocks.

Functional requirements and performance criteria​

The MDD400 is a self-contained, bus-powered NMEA 2000 display node. The board-level requirements below drove the architecture; each is decomposed into per-circuit objectives on the subsystem pages (the Functional specification and design objectives section of each).

System functional requirements

  • Draw all power and data from a single NMEA 2000 Micro-C connection — no external supply or auxiliary cabling.
  • Present network data on a helm-mounted 4.0″ capacitive-touch display that stays legible in sunlight.
  • Monitor its own bus power (voltage / current), ambient light (for auto-brightness), and board temperature (for thermal protection), and provide audible alerting.
  • Survive the marine NMEA 2000 electrical environment — bus transients, surge, reverse polarity, and over-voltage — without damage.
  • Maintain four isolated ground domains, crossing boundaries only through defined isolators (opto-isolated legacy serial; bus-referenced, non-isolated CAN).
  • Optionally bridge a single-wire 12 V legacy serial protocol and NMEA 0183 (developer / kit tiers only).

Performance criteria (design targets)

CriterionTargetBasis
Supply input9–16 V DC from the N2K backboneNMEA 2000 network voltage range
Board current budget~250 mA typical / ~500 mA peak (design target)N2K LEN allocation; to be validated once Wi-Fi firmware exists
Operating temperature−10 °C to +70 °C (target)Marine helm environment; pending qualification
Bus robustnessSurvive bus transients, surge, reverse polarity, and over-voltageMarine electrical environment
CAN physical layerISO 11898-2 at 250 kbpsNMEA 2000
Conformance targetsCE RED 2014/53/EU, UKCA, FCC Part 15, RoHS, NMEA 2000Commercial-release compliance

The per-circuit pages carry the detailed objectives and the calculations that verify them; this section is the system-level parent they trace to.

Power flow​

Power enters on the NMEA 2000 backbone through a single 5-pin Micro-C connector at the bus-side panel. It travels through three stages before reaching the digital and display rails:

  1. CAN bus input protection — TVS clamp, MOV, reverse-polarity Schottky, resettable fuse, two-stage LC EMI filter, and over-voltage cut-off MOSFET. Documented on the CAN Bus Power page.
  2. Synchronous buck conversion — two LMR51610 buck converters generate the regulated VCC (3.3 V) digital rail and the VDD (5.0 V) display / buzzer rail from the protected NMEA 2000 supply. Both converters live in a moat-bounded F.Cu / B.Cu GNDREF island that contains the switching return currents. Documented on the Power Supplies page.
  3. Digital and display distribution — VCC feeds the ESP32 module, the three I²C sensors, the CAN transceiver, and the legacy-serial RX/TX paths. VDD feeds the display interface (through a firmware-controlled high-side P-MOSFET switch, with FB3 EMI conditioning) and the buzzer driver (through a similar P-MOSFET / NPN gate-driver combination with output low-pass filtering). Documented on the Display Interface and Buzzer Driver pages.

The VCC distribution exploits a deliberate VCC – GNDREF – GNDREF – VCC plane-pair stack-up across the digital domain: F.Cu and B.Cu carry VCC pour, and the two inner layers carry unbroken GNDREF. This creates two distributed VCC↔GNDREF plane-pair capacitors that decouple the rail at GHz frequencies with no parasitic inductance and no ESR — explained in detail on the Power Supplies page and exploited specifically on the ESP32 Module page (force-commutated daisy-chain bypass cluster at U3 pad 2).

VDD has no similar plane-pair treatment — it's used only by the display and buzzer, both of which have local bulk + HF bypass at their consumer ends.

Data flow​

The ESP32-S3-WROOM-1-N16R8 module (U3 on the ESP32 Module page) is the system controller. All inter-block data signals fan out from U3 over hierarchical labels on the schematic:

  • NMEA 2000 (CAN) — TWAI_TX / TWAI_RX / TWAI_EN drive the SN65HVD234 transceiver on the CAN Transceiver page, which connects to NET-H / NET-L on the Micro-C connector through a two-stage common-mode filter and split-termination network. The ESP32-S3 TWAI peripheral handles CAN frame transmission and reception; firmware decodes incoming PGNs and emits outgoing status/alert PGNs.
  • DWIN display — DISP_TX / DISP_RX / DISP_EN drive the DWIN DMG48480F040 4.0-inch capacitive-touch panel over UART2 using the DGUS II proprietary serial protocol. All rendering, animation, and touch-event processing run on the display's internal T5L SoC; the ESP32 acts only as a DGUS II host. DISP_EN gives firmware control over the display's power state (default off; firmware-controlled hard reset path). Documented on the Display Interface page.
  • I²C sensor bus — I2C_SCL / I2C_SDA at I²C Standard mode (100 kHz) connect three slaves: INA219 Power Monitor at 0x40 (NMEA 2000 bus current and voltage); OPT3004 Ambient Light Sensor at 0x44 (drives the firmware brightness loop); TMP112 Temperature Sensor at 0x48 (drives the three-tier thermal protection: alert / derate / graceful shutdown). Bus pull-ups (R1 / R2 / R3) physically live on the i2c_sensors sub-sheet but logically belong with the MCU — documented on the ESP32 Module page.
  • Audio output — AUDIO_PWM drives the Buzzer Driver page's two-transistor high-side switch. The ESP32-S3 LEDC peripheral generates the audio-frequency PWM; the R10 / C12 / R9 low-pass filter (f−3dB ≈ 7.2 kHz) shapes the PWM into clean alert tones. The buzzer is the last audible warning before the graceful-shutdown event powers the display down via DISP_EN.
  • Status LED — LED_EN drives the LED Indicator page's PNP high-side switch. Default-on by hardware bias so the LED is on as soon as VCC is stable, before firmware boots. It is a rear-facing service indicator for technician bring-up / fault-finding — not visible once the unit is bulkhead-mounted — confirming power-good independently of the MCU.
  • Programming interface — ESP_TX / ESP_RX / ESP_EN / ESP_BOOT terminate at the Programming Socket page's J1 ESP-PROG IDC header (developer/kit build) or the J1 THT pad footprint (production pogo-pin programming, R22 zero-ohm link in place of the LDO chain).
  • Legacy serial (optional) — ST_TX / ST_RX / ST_EN drive opto-isolated transmit and receive paths to the legacy serial backbone (single-wire 12 V protocol and NMEA 0183 receive-only operation). Documented on the Legacy Serial Interface page.

Ground domain map​

The MDD400 has four electrically isolated ground domains, each with its own pour and isolation creepage gap. Crossing a domain boundary is always via a defined isolator (transformer-coupled CAN transceiver, opto-coupler for legacy serial, or a regulator's input-output isolation).

DomainReferenceScopeCrossing devices
CAN domainGNDCNMEA 2000 input — Micro-C connector, input protection (TVS / MOV / fuse / Schottky), EMI filter, OVP MOSFET. References the NMEA 2000 NET-C.NMEA 2000 bus differential coupling crosses to GNDREF via the SN65HVD234 CAN transceiver's internal isolation.
SMPS domainGNDSMPSBuck-converter switching island — LMR51610 cores, switching inductors, hot loops. Bounded by a copper-pour moat on all four layers.Crosses to GNDREF via FB1 / FB2 ferrite beads on the output rails (low-frequency continuous, high-frequency blocked).
DIGITAL domainGNDREFEverything downstream of the SMPS — ESP32, sensors, display, buzzer, status LED. The main return for the VCC plane-pair stack-up across the digital area.Crosses to GNDS via TLP2309 opto-couplers in the legacy serial paths.
LEGACY IO domain (optional, populated for legacy-serial builds)GNDSGalvanically isolated legacy serial backbone — single-wire 12 V signalling and NMEA 0183 receive. Has its own isolated 12 V supply (ZXTR2012FF LDO on the Legacy Serial RX sheet).Crosses to GNDREF only via TLP2309 opto-couplers; no DC continuity.

The board enforces these boundaries with 1.4 mm creepage gaps across each isolation line and copper-free zones across all four layers within those gaps. Layout violations across an isolation boundary would break the galvanic separation — the design-intent notes on each isolation-crossing page flag this for any future PCB cleanup.

Subsystems​

Each block on the schematic block diagram above maps to one or more docs pages:

FunctionDocs pageKiCad sheetWhat it covers
NMEA 2000 input protectionCAN Bus Powercan_bus_power.kicad_schTVS / MOV / fuse / reverse-polarity diode; two-stage LC EMI filter; OVP MOSFET cut-off
3.3 V + 5.0 V buck conversionPower Suppliespower_supplies.kicad_schTwo LMR51610 buck converters; moat-bounded SMPS island; VCC plane-pair distribution; domain isolation boundaries
CAN transceiverCAN Transceivercan_transceiver.kicad_schSN65HVD234 transceiver; CAN common-mode filter; split-termination + TVS protection on NET-H / NET-L
MCU + VCC bypass + I²C bus pull-upsESP32 Moduleesp32_module.kicad_sch + i2c_sensors.kicad_schESP32-S3-WROOM-1-N16R8; force-commutated VCC bypass at U3 pad 2; EN / BOOT control-line networks; I²C bus pull-ups (R1 / R2 / R3)
Programming hardwareProgramming Socketesp32_module.kicad_schJ1 ESP-PROG IDC header; HT7833 LDO + dual-Schottky-OR'd chain (D3 / D4 / D5); production-variant R22 zero-ohm bridge
Status LEDLED Indicatoresp32_module.kicad_schRear-facing service LED — Q1 PNP high-side switch driving D2 amber LED via LED_EN; default-on bias
Power monitorPower Monitori2c_sensors.kicad_schINA219 at 0x40; 330 mΩ shunt R33 in series with post-OVP supply; firmware-driven Power display page
Ambient light sensorAmbient Light Sensori2c_sensors.kicad_schOPT3004 at 0x44; photopic spectral response; drives firmware brightness loop
Temperature sensorTemperature Sensori2c_sensors.kicad_schTMP112 at 0x48; PCB + display thermal coupling on B.Cu; three-tier firmware protection (alert / derate / shutdown)
DisplayDisplay Interfacedisplay_interface.kicad_schDWIN DMG48480F040 4.0-inch DGUS II display; high-side P-MOSFET switched VDSP rail; 50-pin FPC connector
Audio alertsBuzzer Driverbuzzer_driver.kicad_schMLT-8530 passive electromagnetic transducer; high-side P-MOSFET drive via NPN gate driver; output LP filter; flyback Schottky
Legacy serialLegacy Serial Interfacelegacy_serial_rx.kicad_sch + legacy_serial_tx.kicad_schOpto-isolated transmit and receive paths to single-wire 12 V protocols and NMEA 0183; ZXTR2012FF isolated supply; TLP2309 opto-couplers
PCB markings & compliancePCB Markings & Compliancepcb_markings.kicad_schSilkscreen marks (CE / UKCA / FCC / RoHS / EFUP); board-identity copper; Scadys logo; product-docs QR; fiducial markers; PCB stackup detail; mounting and board outline

PCB stack-up and layer allocation​

The MDD400 V2.9 PCB is a four-layer design manufactured to IPC-6012 Class 2, with ENIG surface finish and dark blue solder mask. The stack-up is asymmetric in copper weight (signal layers at 0.5 oz / 17.5 µm; inner layers at 1 oz / 35 µm) and the layer roles change region-by-region across the board:

Layer#TypeThicknessRole
F.Cu0Signal17.5 µm (0.5 oz)Component layer; VCC pour in the digital region; GNDREF moat-bounded fills under SMPS and isolation islands; routed signals
In1.Cu4Power35 µm (1 oz)Unbroken GNDREF in the digital region (one half of the plane pair); GNDREF moat inside the SMPS island
In2.Cu6Power35 µm (1 oz)Unbroken GNDREF in the digital region (other half of the plane pair); domain-dependent fills elsewhere
B.Cu2Signal17.5 µm (0.5 oz)VCC pour in the digital region; GNDREF fills under SMPS and isolation islands; signal routing

In the digital region (ESP32 module, sensors, display power switch, buzzer driver), F.Cu and B.Cu carry VCC pour; In1.Cu and In2.Cu carry unbroken GNDREF. The two VCC↔GNDREF plane pairs (F.Cu↔In1.Cu and In2.Cu↔B.Cu) separated by 0.1855 mm prepreg form a distributed VCC bypass capacitor across the whole digital area — no parasitic inductance, no ESR, effective up to GHz frequencies. This is what makes the force-commutated three-cap daisy-chain at U3 pad 2 sufficient for the antenna's 2.4 GHz fundamental: above the discrete caps' package ESL, the plane pair takes over.

In the SMPS island (LMR51610 cores, switching nodes, hot loops), all four layers carry GNDREF with a copper-keepout moat surrounding the island. Switching return currents are contained inside the moat; the only escape path is through B.Cu, which adds enough inductance to attenuate HF coupling into the rest of the board. Documented in detail on the Power Supplies page.

Across isolation boundaries (CAN-bus side to digital domain; legacy-serial side to digital domain), all four layers carry copper-free 1.4 mm creepage gaps. Crossing devices (transceiver, opto-couplers, ferrite beads, regulators with isolated I/O) are the only DC paths between domains.

EMC layout philosophy​

The MDD400 layout follows three principles, each grounded in a specific reference:

  1. Confine the switching converters. Per the Monolithic Power Systems EMI webinar (Practical Grounding and Layout), every buck-converter SW node, input hot loop, and output hot loop is kept inside the SMPS island. The island is surrounded by a 0.4 mm copper-keepout moat on F.Cu and B.Cu; the inner GNDREF planes provide a containment cage. Documented on the Power Supplies page.

  2. Use the VCC↔GNDREF plane pair as the primary GHz-band decoupling. Discrete bypass caps handle frequencies up to their package self-resonance (~100 MHz for 0603 X7R, higher for C0G). Above that, the plane pair takes over — provided the digital area's F.Cu / B.Cu pours stay as VCC (not GNDREF) so the plane-pair geometry is preserved. The moat-bounded GNDREF on F.Cu / B.Cu is therefore only under the SMPS, CAN-bus-power, and isolation islands; extending it into the digital area would break the plane-pair capacitance.

  3. Preserve module pre-certification with antenna keep-out. The ESP32-S3-WROOM-1's FCC / CE / IC pre-certification is contingent on a 3 mm copper-free area in the antenna projection. The MDD400 layout exceeds this by 2× — ≥ 6.3 mm clearance on F.Cu, ≥ 10.9 mm on B.Cu, with the antenna aligned to a dedicated board-edge slot. Documented on the ESP32 Module page.

The display backlight switching converter (internal to the DWIN module) is the secondary noise source. FB3 (BLM31KN601SN1L) on the VDSP rail between Q4 drain and the C37 / C38 cluster contains the display-side conducted noise behind a ferrite bead — see the Display Interface page.

References​