Tasks
Hardware version
CANBench Duo v1.1 — Fabricated prototype, sole built unit. V1.1 is electrically identical to the V1.2 schematic refresh but predates the InvenTree symbol-library migration; the schematic component metadata reflects legacy SCADYS naming. Testing and bench validation reference this V1.1 hardware. Live task list for the V1.1 hardware validation and the next-version (V1.3) backlog. Underlying data: tasks.json — hand-maintained, edited as work progresses.
Other versions: v1.2 — schematic refresh (next version)
Every actionable task for CANBench Duo V1.1 — validation work against the V1.1 fabricated hardware + the next-version (V1.3) backlog — across the relevant product domains (hardware, housing, compliance; no firmware since the instrument is fully passive). Click a row to expand details; click a column header to sort; hover any badge for help. See Legend below for full field meanings, or Editing workflow for how to update entries.
27
Total
1
Done
0
In progress
25
To do
0
Blocked
0
Deferred
By kind:Verification 14Next version 13
By category:Hardware 21Housing 2Compliance 4
Status:Kind:Category:Sub-circuit / module:
| Kind ▲ | Category | Sub-circuit / module | Task / description | Status | Date | Result | |
|---|---|---|---|---|---|---|---|
| Verification v1.1 | Hardware | CAN Common-Mode Port | VNA CMRR vs frequency on CAN CM port Drive the CAN-H / CAN-L pair as a common-mode pair and as a differential-mode pair across 150 kHz – 108 MHz. Measure J6 SMA output for each drive mode. CMRR = 20·log₁₀(V_DM/V_CM). Confirm the calculated CMRR bound (≈ 60 dB at DC, falling to < 30 dB at 108 MHz). Identify the dominant degradation mechanism — resistor matching, X7R coupling cap matching, or PCB trace asymmetry. | To do | — | — | |
| Verification v1.1 | Hardware | Documentation | Engineer review of authored V1.1 docs Read every page under docs.scadys.io/canbench-duo/v1.1/ in detail (index, quick-reference, circuit-design overview + six per-circuit pages, housing, compliance, tasks page). Catch factual errors, design-intent misrepresentations, regulatory-claim wording issues, anything that needs rewording for tone or technical accuracy. Hand back a punch list against the specific page paths. | To do | — | — | |
| Verification v1.1 | Hardware | LISN Measurement Ports | IEC 61000-4-2 ESD characterisation at SMAs and M12 Apply IEC 61000-4-2 ESD pulses to the three SMA outputs (J2 / J4 / J6) and the M12 connector (J10) at the design target of ±8 kV air discharge and ±6 kV contact discharge. Confirm the protection cascade clamps the residual transient at the analyser side to ≤ +10 dBm into 50 Ω. No damage to TPAZ1023, clamp diodes, or measurement-port resistors. | To do | — | — | |
| Verification v1.1 | Hardware | LISN Measurement Ports | LISN+ / LISN− symmetry comparison Drive a known DUT and compare the LISN+ and LISN− SMA captures simultaneously (or with strict cable-swap repeatability). Validate that the mirror-symmetric PCB layout achieves low common-mode-to-differential-mode conversion. Identify any asymmetries traceable to layout (e.g. uneven via density, asymmetric ground returns). | To do | — | — | |
| Verification v1.1 | Hardware | LISN Measurement Ports | SPICE S21 of measurement-port chain with PCB parasitics SPICE-simulate the full RF chain (AC-couple → π attenuator → C-L-C high-pass → protection cascade → SMA load) including PCB trace parasitics. Predict the S21 curve and the upper-band-edge return loss for comparison against the VNA measurement. | To do | — | 2026-06-04: analytical two-port (ABCD-cascade) model done as a first pass from the canonical kicad-cli netlist. |S21| ≈ −11.2 dB flat across 150 kHz–108 MHz (0.08 dB ripple), LF −3 dB corner 7.09 kHz, return loss |S22| worst −17.3 dB at 108 MHz (beats −15 dB target). Computed values, not measured. | ▶ |
| Verification v1.1 | Hardware | LISN Measurement Ports | TPAZ1023 TVS datasheet ESD ratings Fetch the Tech Public TPAZ1023-02F datasheet and confirm the part-level ESD ratings (IEC 61000-4-2 air / contact, JEDEC HBM, MM) against the topology-derived design targets. Document the per-channel capacitance and the activation voltage curve. | To do | — | — | |
| Verification v1.1 | Hardware | LISN Measurement Ports | VNA S21 of LISN+ / LISN− ports VNA-sweep S21 for both J2 (LISN+) and J4 (LISN−), 150 kHz – 200 MHz. Confirm the ≈ −10 dB attenuator transfer function across the CISPR 25 measurement band and the return loss at the 108 MHz upper band edge. Compare LISN+ vs LISN− symmetry. | To do | — | — | ▶ |
| Verification v1.1 | Hardware | LISN Supply Path | CISPR 25 baseline noise floor sweep With all three SMA outputs terminated into 50 Ω except the one being measured, sweep 150 kHz – 108 MHz on tinySA ULTRA at the measurement settings (200 Hz RBW, 50 averages). Establish the instrument noise floor — the level below which DUT signatures cannot be resolved. | Done | 2026-06-04 | 2026-06-04: MEASURED on tinySA Ultra (V1.1 board unpowered, J2→tinySA, J4/J6 into 50 Ω, 0 dB atten, no LNA). Flat thermal floor −100 dBm @ 100 kHz RBW, −110 dBm @ 10 kHz RBW (scales ~10 dB/decade — pure thermal, no spurs). No ambient breakthrough 1–150 MHz (not even FM). KEY FINDING: floor rises steeply below ~1 MHz to −67 dBm at the 150 kHz band edge — the tinySA's own LF noise, not the board — which limits low-band sensitivity. Full 150 kHz–150 MHz coverage; evidence in performance_review/noise_floor/. | ▶ |
| Verification v1.1 | Hardware | LISN Supply Path | Murata BLE32 ferrite rated-current datasheet Fetch the full Murata BLE32-series datasheet and confirm the rated continuous current of the as-installed part against the LISN supply path's 4 A continuous design intent. Closes an open datasheet-spec gap on the ferrite. | To do | — | — | |
| Verification v1.1 | Hardware | LISN Supply Path | Noise floor with HT004 LNA — low-band recovery Repeat the baseline noise-floor sweep with the HT004 20 dB LNA inline (J2 → LNA → tinySA). Quantify how much it lowers the overall floor and, specifically, whether it recovers sensitivity in the 150 kHz–1 MHz low band where the bare-tinySA floor rises to −67 dBm. Watch for LNA overload. Determines whether the LNA is needed for low-band conducted-emissions measurement. | To do⛓ 1 | — | — | ▶ |
| Verification v1.1 | Hardware | LISN Supply Path | SPICE LISN ladder impedance with PCB parasitics Run a SPICE simulation of the 5-stage LISN ladder including the as-laid PCB parasitics (per-segment inductance, GNDREF-island capacitance, via inductance). Compare the simulated impedance curve against the analytical jωL for an ideal 5 µH artificial network, identifying any frequency-shaped artefacts (resonances, notches) introduced by the layout. | To do | — | — | |
| Verification v1.1 | Hardware | LISN Supply Path | Thermal characterisation at 4 A continuous Run the LISN at 4 A continuous DC at 25 °C ambient and again at 40 °C ambient. Measure component temperatures (Q2 / Q3 protection FETs, ferrite, ladder inductors, high-current trace runs). Validate the documented derate envelope (4 A @ 25 °C → 3 A @ 40 °C). Identify the thermal-limiting component. | To do | — | — | |
| Verification v1.1 | Hardware | LISN Supply Path | VNA LISN port impedance at DUT bananas VNA-sweep the LISN port impedance presented at the DUT banana sockets (J1 / J3), 150 kHz – 108 MHz. Confirm the LISN presents the expected ~ 5 µH artificial-network impedance at the DUT terminals, not just at the ladder output (C7 / C14 sit ~ 27 mm upstream of J1 / J3 on F.Cu). Result closes the V1.3 question of whether DUT-side HF shunts are necessary. | To do | — | — | |
| Verification v1.1 | Hardware | Power Indicator LED | Power-up Blue-flash duration measurement Capture the indicator-LED behaviour during a clean supply turn-on (no DUT load). Quantify the BLUE-state flash duration as Q2 ramps to full conduction (estimated ~ ms from the Q2 gate-bias RC time constant). Confirm benign duration that does not confuse the user during normal startup. | To do | — | — | |
| Next version v1.3 | Compliance | Compliance | EMC compliance testing at accredited lab Conducted-emissions and radiated-emissions sweeps against the applicable harmonised standards under CE EMC Directive 2014/30/EU. Output: EMC test report kept on file by SCADYS as the responsible economic operator. Gating item for V1.3 public release. | To do | — | — | |
| Next version v1.3 | Compliance | Compliance | RoHS verification of full V1.3 BOM Confirm every component on the V1.3 BOM carries the `ROHS` suffix in InvenTree and that supplier-supplied Material Declaration certificates are on file. The V1.2 BOM already passes this check; carry the verification forward through any V1.3 BOM changes. | To do | — | — | |
| Next version v1.3 | Compliance | Compliance | Sign CE + UKCA Declaration of Conformity Prepare and sign the CE Declaration of Conformity and the UKCA conformity assessment document. Both reference the EMC test report from `compliance-emc-lab-test`. Kept on file by SCADYS as the responsible economic operator. Gating item for V1.3 public release. | To do⛓ 1 | — | — | ▶ |
| Next version v1.3 | Housing | Connectors & Mechanical | Decide V1.3 J8 chassis-bond strategy Decide whether to populate J8 (Keystone 1211 chassis-ground stud) in V1.3, or keep the V1.1 / V1.2 wire-braid-to-faceplate-binding-post strategy unchanged. Trade-off: J8 populated gives a direct screw-down stud bond; binding post gives a tool-free user-facing bond. Both are mutually exclusive in practice (only one bond path is needed). | To do | — | — | |
| Next version v1.3 | Hardware | LISN Measurement Ports | Add ground-via stitching at SMA shells and M12 Increase ground-via density around each SMA shell (J2 / J4 / J6) and the M12 N2K connector body (J10). Recurring gap across the PCB review — V1.1 / V1.2 have sparse stitching that may degrade ESD performance and HF return-current path. Either add stitching in V1.3 or close empirically via the ESD test (`lisn-measurement-ports-esd`). | To do⛓ 1 | — | — | ▶ |
| Next version v1.3 | Hardware | LISN Supply Path | Add HF shunt caps at DUT banana ends Add HF shunt capacitors at the J1 / J3 banana sockets to bypass the ~ 27 mm of `DUT±` rail trace between the LISN ladder output (where C7 / C14 currently sit) and the banana terminals. The trace adds ~ 27 nH of parasitic inductance at the 108 MHz band edge, potentially degrading the LISN impedance presented at the DUT terminals. Final scope contingent on V1.1 VNA measurement (see `lisn-supply-path-vna-port-impedance`). | To do⛓ 1 | — | — | ▶ |
| Next version v1.3 | Hardware | LISN Supply Path | Verify high-current trace widths vs IPC-2152 Extract per-segment trace widths on the `SUPPLY±` / `DUT±` / `VSS±` / `VSF±` nets in the V1.1 .kicad_pcb. Confirm widths ≥ 1.5 mm against IPC-2152 for 1 oz outer-layer copper at 4 A continuous, 30 °C rise. Widen any segment below 1.5 mm in the V1.3 layout, OR derate the continuous-current spec. | To do | — | — | |
| Next version v1.3 | Hardware | PCB Markings | Correct the S7 QR-code URL Replace `docs.scadys.com/mdd400` (clone-leftover from the project's MDD400 fork origin) with the canonical CANBench Duo docs URL. The V1.2 schematic queues the fix; verify it lands in the V1.3 silkscreen artwork. | To do | — | — | |
| Next version v1.3 | Hardware | PCB Markings | Migrate project-local QR / version footprints to SCADYS library Replace `EMCBench CAN-LISN:qr-code` and `EMCBench CAN-LISN:version_knockout` (both project-local) with SCADYS-canonical equivalents in the `SILKS:` library for cross-product consistency. KiCad-hygiene library cleanup item. | To do | — | — | |
| Next version v1.3 | Housing | PCB Markings | Migrate silkscreen F.SilkS → B.SilkS Move the regulatory + identification cluster (S1 / S3 / S4 / S5 / S6 / S7 / S8) from F.SilkS to B.SilkS so the marks face the user-visible top face of the assembled enclosure alongside the laser-etched operational labels. Satisfies the regulatory-visibility requirement at the assembled-product level. | To do | — | — | |
| Next version v1.3 | Compliance | PCB Markings | Upsize CE / UKCA marks to ≥ 5 mm Replace the 3.5 mm CE / UKCA silkscreen footprints with ≥ 5 mm variants per EU Directive 765/2008/EC Annex II and UK SI 696/2008. The PCB (99 × 79 mm) is not size-constrained, so the smaller marks do not qualify for the proportional-reduction exception. | To do | — | — | |
| Next version v1.3 | Hardware | Power Indicator LED | Fix Q1 symbol library mismatch The schematic symbol library declares Q1 as `Transistor - PNP:PNP-SOT323-BC807-000180` (suggesting SOT-323) but the actual installed part is BC807-25 in SOT-23, matching the PCB footprint. Update the symbol library lib_id to match. KiCad-hygiene library cleanup; not a functional blocker on V1.1. | To do | — | — | |
| Next version v1.3 | Hardware | Power Indicator LED | Upsize R1 / R3 to 1206 (0.4 W) Replace the 0805 0.25 W resistors with 1206 0.4 W footprints to improve thermal margin at the 48 V supply ceiling. V1.1 / V1.2 utilisation at 48 V is 84 % of the 0.25 W rating; the upsize brings utilisation to ~ 53 % of the 0.4 W rating. | To do | — | — |
Click any row to expand assignee, dependencies, notes and evidence links. Click any column header to sort. A ⛓ badge next to status indicates the task has dependencies — green = all done, red = some still open.
Legend
Kind
- Verification — measurement / simulation against the V1.1 fabricated hardware (or numerical work against the as-installed component datasheet specs). Closes evidence gaps flagged in the schema-review / pcb-review / performance-review pipeline.
- Next version — design / rework item targeted at V1.3 (the next fabrication). The badge includes the target version (
v1.3).
Category
- Hardware — work against the assembled PCB (most of the current list).
- Firmware — none. The CANBench Duo is a fully passive instrument; there is no firmware.
- Housing — enclosure layer / orientation / chassis-bond items.
- Compliance — EMC lab testing, Declaration of Conformity, RoHS verification, regulatory-mark sizing.
Status
- To do — not yet attempted.
- In progress — being worked on now.
- Done — completed with a recorded result.
- Blocked — can't proceed (waiting on parts, equipment, or upstream dependency).
- Deferred — intentionally postponed to a later campaign or version.
- N/A — no longer relevant (e.g. superseded by a design change).
Dependency chain (⛓ badge)
The ⛓ badge next to a status indicates the task has upstream dependencies. Green = all dependencies are done. Red = some dependencies are still open (the task may need to wait). Expand the row to see the dependency list with each upstream task's status inline.
Editing workflow
Update the JSON file alongside the task execution:
- Change
statusto"in_progress"while working, then"done"when complete. - Fill in
date_completed(ISO format, e.g."2026-06-15") andresult(free-text — e.g."4.7 Ω at 150 kHz, rising to 47 Ω at 1 MHz"or"Failed at 6.2 A — see notes"). - Add
notesfor unexpected behaviour, observations, lessons learned. - Add
assigneeif it's a delegated task (free-text — operator or team name). - Add
dependencies(array of upstream task IDs) if the task can't start until other items complete. - Add
evidenceURLs for VNA traces, SPICE outputs, photos, or test reports (relative paths under/assets/bringup/canbench-duo-v1.1/<task-id>.pngwork; external URLs also work).
How this list is maintained
The list is hand-maintained. It was seeded from the V1.3 hardware fixes and validation work sections of the earlier narrative tasks.md draft, themselves derived from the per-circuit ## Gaps / ## Remaining Gaps blocks in the schema_review/, pcb_review/, and performance_review/ evidence files in D:\GitHub\scadys.io\CANBench-Duo\PCB\CANBench_Duo_V1.1\.
When a per-circuit evidence file gains a new gap, add a matching entry to tasks.json. When an evidence-file gap is reworded, update the matching entry's description to stay in sync. The hardware-repo's evidence pipeline remains the canonical narrative for the why behind each task; this page is the live state tracker.